[33/57,Arm,GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64

Message ID 73484c46-3316-f6c2-7e9a-80453f618567@arm.com
State New
Headers show
Series
  • : Add support for Armv8.1-M Mainline MVE instructions
Related show

Commit Message

Andre Vieira (lists) May 1, 2019, 5:33 p.m.
Hi,

This patch adds support for VSHR, VRSHR, VSLI, VSRI, VREV16, VREV32, and 
VREV64.

gas/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_neon_sli): Accept MVE variants.
	(do_neon_sri): Likewise.
	(do_neon_rev): Likewise.
	(do_neon_rshift_round_imm): Likewise.
         (insns): Likewise.
	* testsuite/gas/arm/mve-vrev-bad.d: New test.
	* testsuite/gas/arm/mve-vrev-bad.l: New test.
	* testsuite/gas/arm/mve-vrev-bad.s: New test.
	* testsuite/gas/arm/mve-vshr-bad.d: New test.
	* testsuite/gas/arm/mve-vshr-bad.l: New test.
	* testsuite/gas/arm/mve-vshr-bad.s: New test.
	* testsuite/gas/arm/mve-vsli-bad.d: New test.
	* testsuite/gas/arm/mve-vsli-bad.l: New test.
	* testsuite/gas/arm/mve-vsli-bad.s: New test.
	* testsuite/gas/arm/mve-vsri-bad.d: New test.
	* testsuite/gas/arm/mve-vsri-bad.l: New test.
	* testsuite/gas/arm/mve-vsri-bad.s: New test.

Patch

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 7ee168120e14abb025483e2e8c4bfd2384d85d34..a249fede42404dfa5978235432a8fc913fa1b13e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17876,9 +17876,23 @@  do_neon_abs_neg (void)
 static void
 do_neon_sli (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
-  struct neon_type_el et = neon_check_type (2, rs,
-    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
+    return;
+
+  enum neon_shape rs;
+  struct neon_type_el et;
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+    {
+      rs = neon_select_shape (NS_QQI, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
+    }
+  else
+    {
+      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+    }
+
+
   int imm = inst.operands[2].imm;
   constraint (imm < 0 || (unsigned)imm >= et.size,
 	      _("immediate out of range for insert"));
@@ -17888,9 +17902,22 @@  do_neon_sli (void)
 static void
 do_neon_sri (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
-  struct neon_type_el et = neon_check_type (2, rs,
-    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
+    return;
+
+  enum neon_shape rs;
+  struct neon_type_el et;
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+    {
+      rs = neon_select_shape (NS_QQI, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
+    }
+  else
+    {
+      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+    }
+
   int imm = inst.operands[2].imm;
   constraint (imm < 1 || (unsigned)imm > et.size,
 	      _("immediate out of range for insert"));
@@ -19115,14 +19142,29 @@  do_neon_ext (void)
 static void
 do_neon_rev (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
+   return;
+
+  enum neon_shape rs;
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+    rs = neon_select_shape (NS_QQ, NS_NULL);
+  else
+    rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+
   struct neon_type_el et = neon_check_type (2, rs,
     N_EQK, N_8 | N_16 | N_32 | N_KEY);
+
   unsigned op = (inst.instruction >> 7) & 3;
   /* N (width of reversed regions) is encoded as part of the bitmask. We
      extract it here to check the elements to be reversed are smaller.
      Otherwise we'd get a reserved instruction.  */
   unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
+
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
+      && inst.operands[0].reg == inst.operands[1].reg)
+    as_tsktsk (_("Warning: 64-bit element size and same destination and source"
+		 " operands makes instruction UNPREDICTABLE"));
+
   gas_assert (elsize != 0);
   constraint (et.size >= elsize,
 	      _("elements must be smaller than reversal region"));
@@ -19666,8 +19708,22 @@  do_mve_movl (void)
 static void
 do_neon_rshift_round_imm (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
-  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
+  if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
+   return;
+
+  enum neon_shape rs;
+  struct neon_type_el et;
+
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+    {
+      rs = neon_select_shape (NS_QQI, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
+    }
+  else
+    {
+      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
+    }
   int imm = inst.operands[2].imm;
 
   /* imm == 0 case is encoded as VMOV for V{R}SHR.  */
@@ -24326,18 +24382,14 @@  static const struct asm_opcode insns[] =
   /* Data processing with two registers and a shift amount.  */
   /* Right shifts, and variants with rounding.
      Types accepted S8 S16 S32 S64 U8 U16 U32 U64.  */
- NUF(vshr,      0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
  NUF(vshrq,     0800010, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
- NUF(vrshr,     0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
  NUF(vrshrq,    0800210, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
  NUF(vsra,      0800110, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
  NUF(vsraq,     0800110, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
  NUF(vrsra,     0800310, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
  NUF(vrsraq,    0800310, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
   /* Shift and insert. Sizes accepted 8 16 32 64.  */
- NUF(vsli,      1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
  NUF(vsliq,     1800510, 3, (RNQ,  oRNQ,  I63), neon_sli),
- NUF(vsri,      1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
  NUF(vsriq,     1800410, 3, (RNQ,  oRNQ,  I64), neon_sri),
   /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64.  */
  NUF(vqshlu,    1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
@@ -24388,11 +24440,8 @@  static const struct asm_opcode insns[] =
 
   /* Two registers, miscellaneous.  */
   /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */
- NUF(vrev64,    1b00000, 2, (RNDQ, RNDQ),     neon_rev),
  NUF(vrev64q,   1b00000, 2, (RNQ,  RNQ),      neon_rev),
- NUF(vrev32,    1b00080, 2, (RNDQ, RNDQ),     neon_rev),
  NUF(vrev32q,   1b00080, 2, (RNQ,  RNQ),      neon_rev),
- NUF(vrev16,    1b00100, 2, (RNDQ, RNDQ),     neon_rev),
  NUF(vrev16q,   1b00100, 2, (RNQ,  RNQ),      neon_rev),
   /* Vector replicate. Sizes 8 16 32.  */
  nCE(vdupq,     _vdup,    2, (RNQ,  RR_RNSC),  neon_dup),
@@ -25112,6 +25161,13 @@  static const struct asm_opcode insns[] =
  mnUF(vqrdmulh,  _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
  MNUF(vqrshl,    0000510,  3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
  MNUF(vrshl,     0000500,  3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
+ MNUF(vshr,      0800010,  3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
+ MNUF(vrshr,     0800210,  3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
+ MNUF(vsli,      1800510,  3, (RNDQMQ, oRNDQMQ, I63),  neon_sli),
+ MNUF(vsri,      1800410,  3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
+ MNUF(vrev64,    1b00000,  2, (RNDQMQ, RNDQMQ),     neon_rev),
+ MNUF(vrev32,    1b00080,  2, (RNDQMQ, RNDQMQ),     neon_rev),
+ MNUF(vrev16,    1b00100,  2, (RNDQMQ, RNDQMQ),     neon_rev),
 
 #undef	ARM_VARIANT
 #define ARM_VARIANT & arm_ext_v8_3
diff --git a/gas/testsuite/gas/arm/mve-vrev-bad.d b/gas/testsuite/gas/arm/mve-vrev-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..8051d7bd01d003ce4257894eb90755f13a6d16af
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vrev-bad.d
@@ -0,0 +1,5 @@ 
+#name: bad MVE VREV16, VREV32 and VREV64 instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vrev-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vrev-bad.l b/gas/testsuite/gas/arm/mve-vrev-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..028c2532762284ad7c0fdb4f7fd6a6868f6ed5a8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vrev-bad.l
@@ -0,0 +1,38 @@ 
+[^:]*: Assembler messages:
+[^:]*:10: Error: elements must be smaller than reversal region -- `vrev16.16 q0,q1'
+[^:]*:11: Error: elements must be smaller than reversal region -- `vrev32.32 q0,q1'
+[^:]*:12: Error: elements must be smaller than reversal region -- `vrev64.64 q0,q1'
+[^:]*:13: Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Error: syntax error -- `vrev16eq.8 q0,q1'
+[^:]*:19: Error: syntax error -- `vrev16eq.8 q0,q1'
+[^:]*:21: Error: syntax error -- `vrev16eq.8 q0,q1'
+[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrev16t.8 q0,q1'
+[^:]*:24: Error: instruction missing MVE vector predication code -- `vrev16.8 q0,q1'
+[^:]*:26: Error: syntax error -- `vrev32eq.8 q0,q1'
+[^:]*:27: Error: syntax error -- `vrev32eq.8 q0,q1'
+[^:]*:29: Error: syntax error -- `vrev32eq.8 q0,q1'
+[^:]*:30: Error: vector predicated instruction should be in VPT/VPST block -- `vrev32t.8 q0,q1'
+[^:]*:32: Error: instruction missing MVE vector predication code -- `vrev32.8 q0,q1'
+[^:]*:34: Error: syntax error -- `vrev64eq.8 q0,q1'
+[^:]*:35: Error: syntax error -- `vrev64eq.8 q0,q1'
+[^:]*:37: Error: syntax error -- `vrev64eq.8 q0,q1'
+[^:]*:38: Error: vector predicated instruction should be in VPT/VPST block -- `vrev64t.8 q0,q1'
+[^:]*:40: Error: instruction missing MVE vector predication code -- `vrev64.8 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vrev-bad.s b/gas/testsuite/gas/arm/mve-vrev-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..b1b5acab71d43ef12d4a8d8a9b41006c892733c2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vrev-bad.s
@@ -0,0 +1,40 @@ 
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().8 q0, q1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vrev16.16 q0, q1
+vrev32.32 q0, q1
+vrev64.64 q0, q1
+vrev64.8  q0, q0
+cond vrev16
+cond vrev32
+cond vrev64
+it eq
+vrev16eq.8 q0, q1
+vrev16eq.8 q0, q1
+vpst
+vrev16eq.8 q0, q1
+vrev16t.8 q0, q1
+vpst
+vrev16.8 q0, q1
+it eq
+vrev32eq.8 q0, q1
+vrev32eq.8 q0, q1
+vpst
+vrev32eq.8 q0, q1
+vrev32t.8 q0, q1
+vpst
+vrev32.8 q0, q1
+it eq
+vrev64eq.8 q0, q1
+vrev64eq.8 q0, q1
+vpst
+vrev64eq.8 q0, q1
+vrev64t.8 q0, q1
+vpst
+vrev64.8 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vshr-bad.d b/gas/testsuite/gas/arm/mve-vshr-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..12a9937846b03dd0614304743ccfe368c88e7925
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vshr-bad.d
@@ -0,0 +1,5 @@ 
+#name: bad MVE VSHR and VRSHR instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vshr-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vshr-bad.l b/gas/testsuite/gas/arm/mve-vshr-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..38fb370a6d7dc11ddbefabea0a45f347d277606b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vshr-bad.l
@@ -0,0 +1,33 @@ 
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vshr.s64 q0,q1,#1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vshr.i32 q0,q1,#1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vrshr.u64 q0,q1,#1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vrshr.i32 q0,q1,#1'
+[^:]*:14: Error: immediate out of range for shift -- `vshr.s8 q0,q1,#9'
+[^:]*:15: Error: immediate out of range for shift -- `vshr.u8 q0,q1,#9'
+[^:]*:16: Error: immediate out of range for shift -- `vshr.s16 q0,q1,#17'
+[^:]*:17: Error: immediate out of range for shift -- `vshr.u16 q0,q1,#17'
+[^:]*:18: Error: immediate out of range for shift -- `vshr.s32 q0,q1,#33'
+[^:]*:19: Error: immediate out of range for shift -- `vshr.u32 q0,q1,#33'
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Error: syntax error -- `vshreq.s32 q0,q1,#1'
+[^:]*:24: Error: syntax error -- `vshreq.s32 q0,q1,#1'
+[^:]*:26: Error: syntax error -- `vshreq.s32 q0,q1,#1'
+[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vshrt.s32 q0,q1,#1'
+[^:]*:29: Error: instruction missing MVE vector predication code -- `vshr.s32 q0,q1,#1'
+[^:]*:31: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
+[^:]*:32: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
+[^:]*:34: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrt.s32 q0,q1,#1'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vrshr.s32 q0,q1,#1'
diff --git a/gas/testsuite/gas/arm/mve-vshr-bad.s b/gas/testsuite/gas/arm/mve-vshr-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..2ec9f57121cfc78e16673df3f03b3e11112ae8e8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vshr-bad.s
@@ -0,0 +1,37 @@ 
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s32 q0, q1, #1
+.endr
+.endm
+
+.syntax unified
+.thumb
+vshr.s64 q0, q1, #1
+vshr.i32 q0, q1, #1
+vrshr.u64 q0, q1, #1
+vrshr.i32 q0, q1, #1
+vshr.s8 q0, q1, #9
+vshr.u8 q0, q1, #9
+vshr.s16 q0, q1, #17
+vshr.u16 q0, q1, #17
+vshr.s32 q0, q1, #33
+vshr.u32 q0, q1, #33
+cond vshr
+cond vrshr
+it eq
+vshreq.s32 q0, q1, #1
+vshreq.s32 q0, q1, #1
+vpst
+vshreq.s32 q0, q1, #1
+vshrt.s32 q0, q1, #1
+vpst
+vshr.s32 q0, q1, #1
+it eq
+vrshreq.s32 q0, q1, #1
+vrshreq.s32 q0, q1, #1
+vpst
+vrshreq.s32 q0, q1, #1
+vrshrt.s32 q0, q1, #1
+vpst
+vrshr.s32 q0, q1, #1
diff --git a/gas/testsuite/gas/arm/mve-vsli-bad.d b/gas/testsuite/gas/arm/mve-vsli-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..a0a9a2a588209350f4d7d6c89b9a25871bd2d55b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vsli-bad.d
@@ -0,0 +1,5 @@ 
+#name: bad MVE VSLI instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vsli-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vsli-bad.l b/gas/testsuite/gas/arm/mve-vsli-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..bde2a6d23b4df3b1ed05e83c6caea4ea0f067154
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vsli-bad.l
@@ -0,0 +1,16 @@ 
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vsli.64 q0,q1,#1'
+[^:]*:11: Error: immediate out of range for insert -- `vsli.8 q0,q1,#8'
+[^:]*:12: Error: immediate out of range for insert -- `vsli.16 q0,q1,#16'
+[^:]*:13: Error: immediate out of range for insert -- `vsli.32 q0,q1,#32'
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:16: Error: syntax error -- `vslieq.8 q0,q1,#2'
+[^:]*:17: Error: syntax error -- `vslieq.8 q0,q1,#2'
+[^:]*:19: Error: syntax error -- `vslieq.8 q0,q1,#2'
+[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vslit.8 q0,q1,#2'
+[^:]*:22: Error: instruction missing MVE vector predication code -- `vsli.8 q0,q1,#2'
diff --git a/gas/testsuite/gas/arm/mve-vsli-bad.s b/gas/testsuite/gas/arm/mve-vsli-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..0bb17830cc32f3582a76a3f30afbcbbc794f35e1
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vsli-bad.s
@@ -0,0 +1,22 @@ 
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vsli.16 q0, q1, #4
+.endr
+.endm
+
+.syntax unified
+.thumb
+vsli.64 q0, q1, #1
+vsli.8 q0, q1, #8
+vsli.16 q0, q1, #16
+vsli.32 q0, q1, #32
+cond
+it eq
+vslieq.8 q0, q1, #2
+vslieq.8 q0, q1, #2
+vpst
+vslieq.8 q0, q1, #2
+vslit.8 q0, q1, #2
+vpst
+vsli.8 q0, q1, #2
diff --git a/gas/testsuite/gas/arm/mve-vsri-bad.d b/gas/testsuite/gas/arm/mve-vsri-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..77e0a24a053d57d66983eb7abcfd96b83919619d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vsri-bad.d
@@ -0,0 +1,5 @@ 
+#name: bad MVE VSRI instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vsri-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vsri-bad.l b/gas/testsuite/gas/arm/mve-vsri-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..1d7df2072b5d5e1233c4e535d89e6e1b43ee4e5c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vsri-bad.l
@@ -0,0 +1,19 @@ 
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vsri.64 q0,q1,#1'
+[^:]*:11: Error: immediate out of range for insert -- `vsri.8 q0,q1,#0'
+[^:]*:12: Error: immediate out of range for insert -- `vsri.8 q0,q1,#9'
+[^:]*:13: Error: immediate out of range for insert -- `vsri.16 q0,q1,#0'
+[^:]*:14: Error: immediate out of range for insert -- `vsri.16 q0,q1,#17'
+[^:]*:15: Error: immediate out of range for insert -- `vsri.32 q0,q1,#0'
+[^:]*:16: Error: immediate out of range for insert -- `vsri.32 q0,q1,#33'
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vsrieq.8 q0,q1,#2'
+[^:]*:20: Error: syntax error -- `vsrieq.8 q0,q1,#2'
+[^:]*:22: Error: syntax error -- `vsrieq.8 q0,q1,#2'
+[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vsrit.8 q0,q1,#2'
+[^:]*:25: Error: instruction missing MVE vector predication code -- `vsri.8 q0,q1,#2'
diff --git a/gas/testsuite/gas/arm/mve-vsri-bad.s b/gas/testsuite/gas/arm/mve-vsri-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..4f07014f6321716b6ae1f3c96fadcf7555b97a4f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vsri-bad.s
@@ -0,0 +1,26 @@ 
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vsri.16 q0, q1, #4
+.endr
+.endm
+
+.syntax unified
+.thumb
+vsri.64 q0, q1, #1
+vsri.8 q0, q1, #0
+vsri.8 q0, q1, #9
+vsri.16 q0, q1, #0
+vsri.16 q0, q1, #17
+vsri.32 q0, q1, #0
+vsri.32 q0, q1, #33
+cond
+it eq
+vsrieq.8 q0, q1, #2
+vsrieq.8 q0, q1, #2
+vpst
+vsrieq.8 q0, q1, #2
+vsrit.8 q0, q1, #2
+vpst
+vsri.8 q0, q1, #2
+