[6/57,Arm,GAS] Add support for MVE instructions: vst/vld{2,4}

Message ID d283104a-a304-4693-18fe-edd7e36956be@arm.com
State New
Headers show
Series
  • : Add support for Armv8.1-M Mainline MVE instructions
Related show

Commit Message

Andre Vieira (lists) May 1, 2019, 5 p.m.
Hi,

This patch adds support for the MVE VLD/VST2[01] and VLD/VST4[0-3] 
instructions.  It reuses NEON's vector list parsing infrastructure with 
some modifications.


gas/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN.
	(BAD_EL_TYPE): New error message.
	(parse_neon_el_struct_list): Adapt to be able to accept MVE variant.
	(parse_address_main): Likewise.
         (group_reloc_type): Add GROUP_MVE.
	(enum operand_parse_code): Add new operands.
	(parse_operands): Handle new operands.
	(M_MNEM_vst20, M_MNEM_vst21, M_MNEM_vst40, M_MNEM_vst41, M_MNEM_vst42,
         M_MNEM_vst43, M_MNEM_vld20, M_MNEM_vld21, M_MNEM_vld40, 
M_MNEM_vld41,
         M_MNEM_vld42, M_MNEM_vld43): New encodings.
	(do_mve_vst_vld): New encoding function.
	(do_neon_ld_st_interleave): Use BAD_EL_TYPE.
	(it_fsm_pre_encode): Handle new it_instruction_type
	(handle_pred_state):
	* testsuite/gas/arm/mve-vstld-bad.d: New test.
	* testsuite/gas/arm/mve-vstld-bad.l: New test.
	* testsuite/gas/arm/mve-vstld-bad.s: New test.

Patch

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4db934c8594f6660baff7e21c925d4b819e4ccf5..2ce9131957617a8279aec9003e44dabe01c90342 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -465,8 +465,9 @@  enum pred_instruction_type
 			      i.e. BKPT and NOP.  */
    IT_INSN,		   /* The IT insn has been parsed.  */
    VPT_INSN,		   /* The VPT/VPST insn has been parsed.  */
-   MVE_OUTSIDE_PRED_INSN   /* Instruction to indicate a MVE instruction without
+   MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
 			      a predication code.  */
+   MVE_UNPREDICABLE_INSN   /* MVE instruction that is non-predicable.  */
 };
 
 /* The maximum number of operands we need.  */
@@ -860,7 +861,7 @@  struct asm_opcode
 #define BAD_OVERLAP	_("registers may not be the same")
 #define BAD_HIREG	_("lo register required")
 #define BAD_THUMB32	_("instruction not supported in Thumb16 mode")
-#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
+#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode")
 #define BAD_BRANCH	_("branch must be last instruction in IT block")
 #define BAD_BRANCH_OFF	_("branch out of range or not a multiple of 2")
 #define BAD_NOT_IT	_("instruction not allowed in IT block")
@@ -895,6 +896,7 @@  struct asm_opcode
     " use a valid -march or -mcpu option.")
 #define BAD_MVE_SRCDEST	_("Warning: 32-bit element size and same destination "\
 			  "and source operands makes instruction UNPREDICTABLE")
+#define BAD_EL_TYPE	_("bad element type for instruction")
 
 static struct hash_control * arm_ops_hsh;
 static struct hash_control * arm_cond_hsh;
@@ -2214,6 +2216,7 @@  neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
 
 static int
 parse_neon_el_struct_list (char **str, unsigned *pbase,
+			   int mve,
 			   struct neon_type_el *eltype)
 {
   char *ptr = *str;
@@ -2223,7 +2226,8 @@  parse_neon_el_struct_list (char **str, unsigned *pbase,
   int lane = -1;
   int leading_brace = 0;
   enum arm_reg_type rtype = REG_TYPE_NDQ;
-  const char *const incr_error = _("register stride must be 1 or 2");
+  const char *const incr_error = mve ? _("register stride must be 1") :
+    _("register stride must be 1 or 2");
   const char *const type_error = _("mismatched element/structure types in list");
   struct neon_typed_alias firsttype;
   firsttype.defined = 0;
@@ -2237,6 +2241,8 @@  parse_neon_el_struct_list (char **str, unsigned *pbase,
   do
     {
       struct neon_typed_alias atype;
+      if (mve)
+	rtype = REG_TYPE_MQ;
       int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
 
       if (getreg == FAIL)
@@ -2344,7 +2350,7 @@  parse_neon_el_struct_list (char **str, unsigned *pbase,
     lane = NEON_INTERLEAVE_LANES;
 
   /* Sanity check.  */
-  if (lane == -1 || base_reg == -1 || count < 1 || count > 4
+  if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
       || (count > 1 && reg_incr == -1))
     {
       first_error (_("error parsing element/structure list"));
@@ -5489,7 +5495,8 @@  typedef enum
 
   GROUP_LDR,
   GROUP_LDRS,
-  GROUP_LDC
+  GROUP_LDC,
+  GROUP_MVE
 } group_reloc_type;
 
 static struct group_reloc_table_entry group_reloc_table[] =
@@ -5742,7 +5749,10 @@  parse_address_main (char **str, int i, int group_relocations,
 
   if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
     {
-      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+      if (group_type == GROUP_MVE)
+	inst.error = BAD_ADDR_MODE;
+      else
+	inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
       return PARSE_OPERAND_FAIL;
     }
   inst.operands[i].reg = reg;
@@ -6750,6 +6760,8 @@  enum operand_parse_code
   OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
   OP_NSTRLST,   /* Neon element/structure list */
   OP_VRSDVLST,  /* VFP single or double-precision register list and VPR */
+  OP_MSTRLST2,	/* MVE vector list with two elements.  */
+  OP_MSTRLST4,	/* MVE vector list with four elements.  */
 
   OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
   OP_RVSD_I0,	/* VFP S or D reg, or immediate zero.  */
@@ -6790,6 +6802,7 @@  enum operand_parse_code
   OP_SH,	/* shifter operand */
   OP_SHG,	/* shifter operand with possible group relocation */
   OP_ADDR,	/* Memory address expression (any mode) */
+  OP_ADDRMVE,	/* Memory address expression for MVE's VSTR/VLDR.  */
   OP_ADDRGLDR,	/* Mem addr expr (any mode) with possible LDR group reloc */
   OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
   OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
@@ -7473,12 +7486,23 @@  parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 				    REGLIST_NEON_D, &partial_match);
 	  break;
 
+	case OP_MSTRLST4:
+	case OP_MSTRLST2:
+	  val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
+					   1, &inst.operands[i].vectype);
+	  if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
+	    goto failure;
+	  break;
 	case OP_NSTRLST:
 	  val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
-					   &inst.operands[i].vectype);
+					   0, &inst.operands[i].vectype);
 	  break;
 
 	  /* Addressing modes */
+	case OP_ADDRMVE:
+	  po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
+	  break;
+
 	case OP_ADDR:
 	  po_misc_or_fail (parse_address (&str, i));
 	  break;
@@ -7581,6 +7605,8 @@  parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 	case OP_VRSDVLST:
 	case OP_NRDLST:
 	case OP_NSTRLST:
+	case OP_MSTRLST2:
+	case OP_MSTRLST4:
 	  if (val == FAIL)
 	    goto failure;
 	  inst.operands[i].imm = val;
@@ -13858,6 +13884,18 @@  do_t_loloop (void)
 #define M_MNEM_vmlsdavax  0xeef01e21
 #define M_MNEM_vmullt	0xee011e00
 #define M_MNEM_vmullb	0xee010e00
+#define M_MNEM_vst20	0xfc801e00
+#define M_MNEM_vst21	0xfc801e20
+#define M_MNEM_vst40	0xfc801e01
+#define M_MNEM_vst41	0xfc801e21
+#define M_MNEM_vst42	0xfc801e41
+#define M_MNEM_vst43	0xfc801e61
+#define M_MNEM_vld20	0xfc901e00
+#define M_MNEM_vld21	0xfc901e20
+#define M_MNEM_vld40	0xfc901e01
+#define M_MNEM_vld41	0xfc901e21
+#define M_MNEM_vld42	0xfc901e41
+#define M_MNEM_vld43	0xfc901e61
 
 /* Neon instruction encoder helpers.  */
 
@@ -15705,6 +15743,44 @@  check_simd_pred_availability (int fp, unsigned check)
   return 0;
 }
 
+static void
+do_mve_vst_vld (void)
+{
+  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
+    return;
+
+  constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
+	      || inst.relocs[0].exp.X_add_number != 0
+	      || inst.operands[1].immisreg != 0,
+	      BAD_ADDR_MODE);
+  constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
+  if (inst.operands[1].reg == REG_PC)
+    as_tsktsk (MVE_BAD_PC);
+  else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
+    as_tsktsk (MVE_BAD_SP);
+
+
+  /* These instructions are one of the "exceptions" mentioned in
+     handle_pred_state.  They are MVE instructions that are not VPT compatible
+     and do not accept a VPT code, thus appending such a code is a syntax
+     error.  */
+  if (inst.cond > COND_ALWAYS)
+    first_error (BAD_SYNTAX);
+  /* If we append a scalar condition code we can set this to
+     MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error.  */
+  else if (inst.cond < COND_ALWAYS)
+    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+  else
+    inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
+
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= inst.operands[1].writeback << 21;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
+  inst.is_neon = 1;
+}
+
 static void
 do_neon_dyadic_if_su (void)
 {
@@ -18011,7 +18087,7 @@  do_neon_ld_st_interleave (void)
 
   constraint (typebits == -1, _("bad list type for instruction"));
   constraint (((inst.instruction >> 8) & 3) && et.size == 64,
-	      _("bad element type for instruction"));
+	      BAD_EL_TYPE);
 
   inst.instruction &= ~0xf00;
   inst.instruction |= typebits << 8;
@@ -19374,7 +19450,7 @@  it_fsm_pre_encode (void)
    Specifications say that any non-MVE instruction inside a VPT block is
    UNPREDICTABLE, with the exception of the BKPT instruction.  Whereas most MVE
    instructions are deemed to be UNPREDICTABLE if inside an IT block.  For the
-   few exceptions this will be handled at their respective handler functions.
+   few exceptions we have MVE_UNPREDICABLE_INSN.
    The error messages provided depending on the different combinations possible
    are described in the cases below:
    For 'most' MVE instructions:
@@ -19411,6 +19487,7 @@  handle_pred_state (void)
     case OUTSIDE_PRED_BLOCK:
       switch (inst.pred_insn_type)
 	{
+	case MVE_UNPREDICABLE_INSN:
 	case MVE_OUTSIDE_PRED_INSN:
 	  if (inst.cond < COND_ALWAYS)
 	    {
@@ -19510,6 +19587,7 @@  handle_pred_state (void)
 	{
 	case INSIDE_VPT_INSN:
 	case VPT_INSN:
+	case MVE_UNPREDICABLE_INSN:
 	case MVE_OUTSIDE_PRED_INSN:
 	  gas_assert (0);
 	case OUTSIDE_PRED_INSN:
@@ -19659,6 +19737,9 @@  handle_pred_state (void)
 		    gas_assert (0);
 		  }
 	      }
+	  case MVE_UNPREDICABLE_INSN:
+	    as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
+	    return SUCCESS;
 	  case INSIDE_IT_INSN:
 	    if (inst.cond > COND_ALWAYS)
 	      {
@@ -22858,6 +22939,19 @@  static const struct asm_opcode insns[] =
  mCEF(vmlsdavx,	  _vmlsdavx,	3, (RRe, RMQ, RMQ),		mve_vmladav),
  mCEF(vmlsdavax,  _vmlsdavax,	3, (RRe, RMQ, RMQ),		mve_vmladav),
 
+ mCEF(vst20,	_vst20,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
+ mCEF(vst21,	_vst21,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
+ mCEF(vst40,	_vst40,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vst41,	_vst41,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vst42,	_vst42,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vst43,	_vst43,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vld20,	_vld20,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
+ mCEF(vld21,	_vld21,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
+ mCEF(vld40,	_vld40,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vld41,	_vld41,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vld42,	_vld42,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+ mCEF(vld43,	_vld43,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
+
 #undef  ARM_VARIANT
 #define ARM_VARIANT    & fpu_vfp_ext_v1xd
 #undef  THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/mve-vstld-bad.d b/gas/testsuite/gas/arm/mve-vstld-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..92b9c929ba0f15e8954cd6b2743d1805b4e14fd7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vstld-bad.d
@@ -0,0 +1,5 @@ 
+#name: bad MVE VST2/4 VLD2/4 instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vstld-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vstld-bad.l b/gas/testsuite/gas/arm/mve-vstld-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..3ea47d52728b2e932c601659a3dbd9d7c8d0725f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vstld-bad.l
@@ -0,0 +1,249 @@ 
+[^:]*: Assembler messages:
+[^:]*:3: Error: register stride must be 1 -- `vst20.8 {q0,q2},\[r0\]'
+[^:]*:4: Error: syntax error -- `vst20.8 {q0,q1,q2},\[r0\]'
+[^:]*:5: Error: syntax error -- `vst20.8 {q0},\[r0\]'
+[^:]*:6: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:7: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:8: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:9: Error: register stride must be 1 -- `vst20.8 {q3,q2},\[r0\]'
+[^:]*:10: Error: bad element type for instruction -- `vst20.64 {q0,q1},\[r0\]'
+[^:]*:11: Error: register stride must be 1 -- `vst21.8 {q0,q2},\[r0\]'
+[^:]*:12: Error: syntax error -- `vst21.8 {q0,q1,q2},\[r0\]'
+[^:]*:13: Error: syntax error -- `vst21.8 {q0},\[r0\]'
+[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:16: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:17: Error: register stride must be 1 -- `vst21.8 {q3,q2},\[r0\]'
+[^:]*:18: Error: bad element type for instruction -- `vst21.64 {q0,q1},\[r0\]'
+[^:]*:19: Error: register stride must be 1 -- `vst40.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:20: Error: register stride must be 1 -- `vst40.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:21: Error: register stride must be 1 -- `vst40.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:22: Error: register stride must be 1 -- `vst40.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:23: Error: syntax error -- `vst40.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:24: Error: syntax error -- `vst40.8 {q0,q1,q2},\[r0\]'
+[^:]*:25: Error: syntax error -- `vst40.8 {q0,q1},\[r0\]'
+[^:]*:26: Error: syntax error -- `vst40.8 {q0},\[r0\]'
+[^:]*:27: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:28: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:29: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:30: Error: bad element type for instruction -- `vst40.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:31: Error: register stride must be 1 -- `vst41.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:32: Error: register stride must be 1 -- `vst41.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:33: Error: register stride must be 1 -- `vst41.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:34: Error: register stride must be 1 -- `vst41.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:35: Error: syntax error -- `vst41.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:36: Error: syntax error -- `vst41.8 {q0,q1,q2},\[r0\]'
+[^:]*:37: Error: syntax error -- `vst41.8 {q0,q1},\[r0\]'
+[^:]*:38: Error: syntax error -- `vst41.8 {q0},\[r0\]'
+[^:]*:39: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:40: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:41: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:42: Error: bad element type for instruction -- `vst41.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:43: Error: register stride must be 1 -- `vst42.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:44: Error: register stride must be 1 -- `vst42.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:45: Error: register stride must be 1 -- `vst42.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:46: Error: register stride must be 1 -- `vst42.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:47: Error: syntax error -- `vst42.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:48: Error: syntax error -- `vst42.8 {q0,q1,q2},\[r0\]'
+[^:]*:49: Error: syntax error -- `vst42.8 {q0,q1},\[r0\]'
+[^:]*:50: Error: syntax error -- `vst42.8 {q0},\[r0\]'
+[^:]*:51: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:52: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:53: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:54: Error: bad element type for instruction -- `vst42.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:55: Error: register stride must be 1 -- `vst43.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:56: Error: register stride must be 1 -- `vst43.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:57: Error: register stride must be 1 -- `vst43.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:58: Error: register stride must be 1 -- `vst43.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:59: Error: syntax error -- `vst43.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:60: Error: syntax error -- `vst43.8 {q0,q1,q2},\[r0\]'
+[^:]*:61: Error: syntax error -- `vst43.8 {q0,q1},\[r0\]'
+[^:]*:62: Error: syntax error -- `vst43.8 {q0},\[r0\]'
+[^:]*:63: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:64: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:65: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:66: Error: bad element type for instruction -- `vst43.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:67: Error: selected processor does not support `vst1.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:68: Error: selected processor does not support `vst2.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:69: Error: selected processor does not support `vst3.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:70: Error: selected processor does not support `vst4.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:71: Error: bad instruction `vst23.32 {q0,q1},\[r0\]'
+[^:]*:72: Error: bad instruction `vst44.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:73: Error: register stride must be 1 -- `vld20.8 {q0,q2},\[r0\]'
+[^:]*:74: Error: syntax error -- `vld20.8 {q0,q1,q2},\[r0\]'
+[^:]*:75: Error: syntax error -- `vld20.8 {q0},\[r0\]'
+[^:]*:76: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:77: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:78: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:79: Error: register stride must be 1 -- `vld20.8 {q3,q2},\[r0\]'
+[^:]*:80: Error: bad element type for instruction -- `vld20.64 {q0,q1},\[r0\]'
+[^:]*:81: Error: register stride must be 1 -- `vld21.8 {q0,q2},\[r0\]'
+[^:]*:82: Error: syntax error -- `vld21.8 {q0,q1,q2},\[r0\]'
+[^:]*:83: Error: syntax error -- `vld21.8 {q0},\[r0\]'
+[^:]*:84: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:85: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:86: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:87: Error: register stride must be 1 -- `vld21.8 {q3,q2},\[r0\]'
+[^:]*:88: Error: bad element type for instruction -- `vld21.64 {q0,q1},\[r0\]'
+[^:]*:89: Error: register stride must be 1 -- `vld40.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:90: Error: register stride must be 1 -- `vld40.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:91: Error: register stride must be 1 -- `vld40.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:92: Error: register stride must be 1 -- `vld40.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:93: Error: syntax error -- `vld40.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:94: Error: syntax error -- `vld40.8 {q0,q1,q2},\[r0\]'
+[^:]*:95: Error: syntax error -- `vld40.8 {q0,q1},\[r0\]'
+[^:]*:96: Error: syntax error -- `vld40.8 {q0},\[r0\]'
+[^:]*:97: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:98: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:99: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:100: Error: bad element type for instruction -- `vld40.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:101: Error: register stride must be 1 -- `vld41.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:102: Error: register stride must be 1 -- `vld41.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:103: Error: register stride must be 1 -- `vld41.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:104: Error: register stride must be 1 -- `vld41.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:105: Error: syntax error -- `vld41.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:106: Error: syntax error -- `vld41.8 {q0,q1,q2},\[r0\]'
+[^:]*:107: Error: syntax error -- `vld41.8 {q0,q1},\[r0\]'
+[^:]*:108: Error: syntax error -- `vld41.8 {q0},\[r0\]'
+[^:]*:109: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:110: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:111: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:112: Error: bad element type for instruction -- `vld41.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:113: Error: register stride must be 1 -- `vld42.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:114: Error: register stride must be 1 -- `vld42.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:115: Error: register stride must be 1 -- `vld42.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:116: Error: register stride must be 1 -- `vld42.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:117: Error: syntax error -- `vld42.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:118: Error: syntax error -- `vld42.8 {q0,q1,q2},\[r0\]'
+[^:]*:119: Error: syntax error -- `vld42.8 {q0,q1},\[r0\]'
+[^:]*:120: Error: syntax error -- `vld42.8 {q0},\[r0\]'
+[^:]*:121: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:122: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:123: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:124: Error: bad element type for instruction -- `vld42.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:125: Error: register stride must be 1 -- `vld43.8 {q0,q2,q3,q4},\[r0\]'
+[^:]*:126: Error: register stride must be 1 -- `vld43.8 {q0,q1,q3,q4},\[r0\]'
+[^:]*:127: Error: register stride must be 1 -- `vld43.8 {q0,q1,q2,q4},\[r0\]'
+[^:]*:128: Error: register stride must be 1 -- `vld43.8 {q3,q1,q2,q3},\[r0\]'
+[^:]*:129: Error: syntax error -- `vld43.8 {q0,q1,q2,q3,q4},\[r0\]'
+[^:]*:130: Error: syntax error -- `vld43.8 {q0,q1,q2},\[r0\]'
+[^:]*:131: Error: syntax error -- `vld43.8 {q0,q1},\[r0\]'
+[^:]*:132: Error: syntax error -- `vld43.8 {q0},\[r0\]'
+[^:]*:133: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:134: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:135: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:136: Error: bad element type for instruction -- `vld43.64 {q0,q1,q2,q3},\[r0\]'
+[^:]*:137: Error: selected processor does not support `vld1.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:138: Error: selected processor does not support `vld2.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:139: Error: selected processor does not support `vld3.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:140: Error: selected processor does not support `vld4.8 {q0,q1},\[r0\]' in Thumb mode
+[^:]*:141: Error: bad instruction `vld23.32 {q0,q1},\[r0\]'
+[^:]*:142: Error: bad instruction `vld44.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:167: Error: syntax error -- `vst20t.32 {q0,q1},\[r0\]'
+[^:]*:168: Error: syntax error -- `vst20e.32 {q0,q1},\[r0\]'
+[^:]*:170: Error: syntax error -- `vst21t.32 {q0,q1},\[r0\]'
+[^:]*:171: Error: syntax error -- `vst21e.32 {q0,q1},\[r0\]'
+[^:]*:173: Error: syntax error -- `vst40t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:174: Error: syntax error -- `vst40e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:176: Error: syntax error -- `vst41t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:177: Error: syntax error -- `vst41e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:179: Error: syntax error -- `vst42t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:180: Error: syntax error -- `vst42e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:182: Error: syntax error -- `vst43t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:183: Error: syntax error -- `vst43e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:186: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:188: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:190: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:192: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:194: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:196: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:205: Error: syntax error -- `vld20t.32 {q0,q1},\[r0\]'
+[^:]*:206: Error: syntax error -- `vld20e.32 {q0,q1},\[r0\]'
+[^:]*:208: Error: syntax error -- `vld21t.32 {q0,q1},\[r0\]'
+[^:]*:209: Error: syntax error -- `vld21e.32 {q0,q1},\[r0\]'
+[^:]*:211: Error: syntax error -- `vld40t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:212: Error: syntax error -- `vld40e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:214: Error: syntax error -- `vld41t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:215: Error: syntax error -- `vld41e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:217: Error: syntax error -- `vld42t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:218: Error: syntax error -- `vld42e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:220: Error: syntax error -- `vld43t.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:221: Error: syntax error -- `vld43e.32 {q0,q1,q2,q3},\[r0\]'
+[^:]*:224: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:226: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:228: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:230: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:232: Warning: instruction is UNPREDICTABLE in a VPT block
+[^:]*:234: Warning: instruction is UNPREDICTABLE in a VPT block
diff --git a/gas/testsuite/gas/arm/mve-vstld-bad.s b/gas/testsuite/gas/arm/mve-vstld-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..1a8b0b11f08e150369c918ddf91e1dec7721f1c8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vstld-bad.s
@@ -0,0 +1,234 @@ 
+.syntax unified
+.thumb
+vst20.8 {q0, q2}, [r0]
+vst20.8 {q0, q1, q2}, [r0]
+vst20.8 {q0}, [r0]
+vst20.8 {q0, q1}, [pc]
+vst20.8 {q0, q1}, [pc]!
+vst20.8 {q0, q1}, [sp]!
+vst20.8 {q3, q2}, [r0]
+vst20.64 {q0, q1}, [r0]
+vst21.8 {q0, q2}, [r0]
+vst21.8 {q0, q1, q2}, [r0]
+vst21.8 {q0}, [r0]
+vst21.8 {q0, q1}, [pc]
+vst21.8 {q0, q1}, [pc]!
+vst21.8 {q0, q1}, [sp]!
+vst21.8 {q3, q2}, [r0]
+vst21.64 {q0, q1}, [r0]
+vst40.8 {q0, q2, q3, q4}, [r0]
+vst40.8 {q0, q1, q3, q4}, [r0]
+vst40.8 {q0, q1, q2, q4}, [r0]
+vst40.8 {q3, q1, q2, q3}, [r0]
+vst40.8 {q0, q1, q2, q3, q4}, [r0]
+vst40.8 {q0, q1, q2}, [r0]
+vst40.8 {q0, q1}, [r0]
+vst40.8 {q0}, [r0]
+vst40.8 {q0, q1, q2, q3}, [pc]
+vst40.8 {q0, q1, q2, q3}, [pc]!
+vst40.8 {q0, q1, q2, q3}, [sp]!
+vst40.64 {q0, q1, q2, q3}, [r0]
+vst41.8 {q0, q2, q3, q4}, [r0]
+vst41.8 {q0, q1, q3, q4}, [r0]
+vst41.8 {q0, q1, q2, q4}, [r0]
+vst41.8 {q3, q1, q2, q3}, [r0]
+vst41.8 {q0, q1, q2, q3, q4}, [r0]
+vst41.8 {q0, q1, q2}, [r0]
+vst41.8 {q0, q1}, [r0]
+vst41.8 {q0}, [r0]
+vst41.8 {q0, q1, q2, q3}, [pc]
+vst41.8 {q0, q1, q2, q3}, [pc]!
+vst41.8 {q0, q1, q2, q3}, [sp]!
+vst41.64 {q0, q1, q2, q3}, [r0]
+vst42.8 {q0, q2, q3, q4}, [r0]
+vst42.8 {q0, q1, q3, q4}, [r0]
+vst42.8 {q0, q1, q2, q4}, [r0]
+vst42.8 {q3, q1, q2, q3}, [r0]
+vst42.8 {q0, q1, q2, q3, q4}, [r0]
+vst42.8 {q0, q1, q2}, [r0]
+vst42.8 {q0, q1}, [r0]
+vst42.8 {q0}, [r0]
+vst42.8 {q0, q1, q2, q3}, [pc]
+vst42.8 {q0, q1, q2, q3}, [pc]!
+vst42.8 {q0, q1, q2, q3}, [sp]!
+vst42.64 {q0, q1, q2, q3}, [r0]
+vst43.8 {q0, q2, q3, q4}, [r0]
+vst43.8 {q0, q1, q3, q4}, [r0]
+vst43.8 {q0, q1, q2, q4}, [r0]
+vst43.8 {q3, q1, q2, q3}, [r0]
+vst43.8 {q0, q1, q2, q3, q4}, [r0]
+vst43.8 {q0, q1, q2}, [r0]
+vst43.8 {q0, q1}, [r0]
+vst43.8 {q0}, [r0]
+vst43.8 {q0, q1, q2, q3}, [pc]
+vst43.8 {q0, q1, q2, q3}, [pc]!
+vst43.8 {q0, q1, q2, q3}, [sp]!
+vst43.64 {q0, q1, q2, q3}, [r0]
+vst1.8 {q0, q1}, [r0]
+vst2.8 {q0, q1}, [r0]
+vst3.8 {q0, q1}, [r0]
+vst4.8 {q0, q1}, [r0]
+vst23.32 {q0, q1}, [r0]
+vst44.32 {q0, q1, q2, q3}, [r0]
+vld20.8 {q0, q2}, [r0]
+vld20.8 {q0, q1, q2}, [r0]
+vld20.8 {q0}, [r0]
+vld20.8 {q0, q1}, [pc]
+vld20.8 {q0, q1}, [pc]!
+vld20.8 {q0, q1}, [sp]!
+vld20.8 {q3, q2}, [r0]
+vld20.64 {q0, q1}, [r0]
+vld21.8 {q0, q2}, [r0]
+vld21.8 {q0, q1, q2}, [r0]
+vld21.8 {q0}, [r0]
+vld21.8 {q0, q1}, [pc]
+vld21.8 {q0, q1}, [pc]!
+vld21.8 {q0, q1}, [sp]!
+vld21.8 {q3, q2}, [r0]
+vld21.64 {q0, q1}, [r0]
+vld40.8 {q0, q2, q3, q4}, [r0]
+vld40.8 {q0, q1, q3, q4}, [r0]
+vld40.8 {q0, q1, q2, q4}, [r0]
+vld40.8 {q3, q1, q2, q3}, [r0]
+vld40.8 {q0, q1, q2, q3, q4}, [r0]
+vld40.8 {q0, q1, q2}, [r0]
+vld40.8 {q0, q1}, [r0]
+vld40.8 {q0}, [r0]
+vld40.8 {q0, q1, q2, q3}, [pc]
+vld40.8 {q0, q1, q2, q3}, [pc]!
+vld40.8 {q0, q1, q2, q3}, [sp]!
+vld40.64 {q0, q1, q2, q3}, [r0]
+vld41.8 {q0, q2, q3, q4}, [r0]
+vld41.8 {q0, q1, q3, q4}, [r0]
+vld41.8 {q0, q1, q2, q4}, [r0]
+vld41.8 {q3, q1, q2, q3}, [r0]
+vld41.8 {q0, q1, q2, q3, q4}, [r0]
+vld41.8 {q0, q1, q2}, [r0]
+vld41.8 {q0, q1}, [r0]
+vld41.8 {q0}, [r0]
+vld41.8 {q0, q1, q2, q3}, [pc]
+vld41.8 {q0, q1, q2, q3}, [pc]!
+vld41.8 {q0, q1, q2, q3}, [sp]!
+vld41.64 {q0, q1, q2, q3}, [r0]
+vld42.8 {q0, q2, q3, q4}, [r0]
+vld42.8 {q0, q1, q3, q4}, [r0]
+vld42.8 {q0, q1, q2, q4}, [r0]
+vld42.8 {q3, q1, q2, q3}, [r0]
+vld42.8 {q0, q1, q2, q3, q4}, [r0]
+vld42.8 {q0, q1, q2}, [r0]
+vld42.8 {q0, q1}, [r0]
+vld42.8 {q0}, [r0]
+vld42.8 {q0, q1, q2, q3}, [pc]
+vld42.8 {q0, q1, q2, q3}, [pc]!
+vld42.8 {q0, q1, q2, q3}, [sp]!
+vld42.64 {q0, q1, q2, q3}, [r0]
+vld43.8 {q0, q2, q3, q4}, [r0]
+vld43.8 {q0, q1, q3, q4}, [r0]
+vld43.8 {q0, q1, q2, q4}, [r0]
+vld43.8 {q3, q1, q2, q3}, [r0]
+vld43.8 {q0, q1, q2, q3, q4}, [r0]
+vld43.8 {q0, q1, q2}, [r0]
+vld43.8 {q0, q1}, [r0]
+vld43.8 {q0}, [r0]
+vld43.8 {q0, q1, q2, q3}, [pc]
+vld43.8 {q0, q1, q2, q3}, [pc]!
+vld43.8 {q0, q1, q2, q3}, [sp]!
+vld43.64 {q0, q1, q2, q3}, [r0]
+vld1.8 {q0, q1}, [r0]
+vld2.8 {q0, q1}, [r0]
+vld3.8 {q0, q1}, [r0]
+vld4.8 {q0, q1}, [r0]
+vld23.32 {q0, q1}, [r0]
+vld44.32 {q0, q1, q2, q3}, [r0]
+
+.macro cond2 op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().32  {q0, q1}, [r0]
+.endr
+.endm
+
+
+
+.macro cond4 op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().32 {q0, q1, q2, q3}, [r0]
+.endr
+.endm
+
+cond2 vst20
+cond2 vst21
+cond4 vst40
+cond4 vst41
+cond4 vst42
+cond4 vst43
+vpste
+vst20t.32 {q0, q1}, [r0]
+vst20e.32 {q0, q1}, [r0]
+vpste
+vst21t.32 {q0, q1}, [r0]
+vst21e.32 {q0, q1}, [r0]
+vpste
+vst40t.32 {q0, q1, q2, q3}, [r0]
+vst40e.32 {q0, q1, q2, q3}, [r0]
+vpste
+vst41t.32 {q0, q1, q2, q3}, [r0]
+vst41e.32 {q0, q1, q2, q3}, [r0]
+vpste
+vst42t.32 {q0, q1, q2, q3}, [r0]
+vst42e.32 {q0, q1, q2, q3}, [r0]
+vpste
+vst43t.32 {q0, q1, q2, q3}, [r0]
+vst43e.32 {q0, q1, q2, q3}, [r0]
+
+vpst
+vst20.32 {q0, q1}, [r0]
+vpst
+vst21.32 {q0, q1}, [r0]
+vpst
+vst40.32 {q0, q1, q2, q3}, [r0]
+vpst
+vst41.32 {q0, q1, q2, q3}, [r0]
+vpst
+vst42.32 {q0, q1, q2, q3}, [r0]
+vpst
+vst43.32 {q0, q1, q2, q3}, [r0]
+
+cond2 vld20
+cond2 vld21
+cond4 vld40
+cond4 vld41
+cond4 vld42
+cond4 vld43
+vpste
+vld20t.32 {q0, q1}, [r0]
+vld20e.32 {q0, q1}, [r0]
+vpste
+vld21t.32 {q0, q1}, [r0]
+vld21e.32 {q0, q1}, [r0]
+vpste
+vld40t.32 {q0, q1, q2, q3}, [r0]
+vld40e.32 {q0, q1, q2, q3}, [r0]
+vpste
+vld41t.32 {q0, q1, q2, q3}, [r0]
+vld41e.32 {q0, q1, q2, q3}, [r0]
+vpste
+vld42t.32 {q0, q1, q2, q3}, [r0]
+vld42e.32 {q0, q1, q2, q3}, [r0]
+vpste
+vld43t.32 {q0, q1, q2, q3}, [r0]
+vld43e.32 {q0, q1, q2, q3}, [r0]
+
+vpst
+vld20.32 {q0, q1}, [r0]
+vpst
+vld21.32 {q0, q1}, [r0]
+vpst
+vld40.32 {q0, q1, q2, q3}, [r0]
+vpst
+vld41.32 {q0, q1, q2, q3}, [r0]
+vpst
+vld42.32 {q0, q1, q2, q3}, [r0]
+vpst
+vld43.32 {q0, q1, q2, q3}, [r0]