[14/16,aarch64] New SVE_SHLIMM_UNPRED_22 operand.

Message ID 1556721866-21052-15-git-send-email-matthew.malcomson@arm.com
State New
Headers show
Series
  • SVE2 binutils instructions for aarch64
Related show

Commit Message

Matthew Malcomson May 1, 2019, 2:44 p.m.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.

gas/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand.

include/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand.

opcodes/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_SHLIMM_UNPRED_22.
	(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
---
 gas/config/tc-aarch64.c  |  1 +
 include/opcode/aarch64.h |  1 +
 opcodes/aarch64-asm-2.c  | 21 +++++++++++----------
 opcodes/aarch64-dis-2.c  | 21 +++++++++++----------
 opcodes/aarch64-opc-2.c  |  1 +
 opcodes/aarch64-opc.c    |  2 ++
 opcodes/aarch64-tbl.h    |  3 +++
 7 files changed, 30 insertions(+), 20 deletions(-)

-- 
2.7.4

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fbe2dcf..9b09cbf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5783,6 +5783,7 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_LIMM_MOV:
 	case AARCH64_OPND_SVE_SHLIMM_PRED:
 	case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+	case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
 	case AARCH64_OPND_SVE_SHRIMM_PRED:
 	case AARCH64_OPND_SVE_SHRIMM_UNPRED:
 	case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2b78e97..ac484ca 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -389,6 +389,7 @@  enum aarch64_opnd
   AARCH64_OPND_SVE_Rn_SP,	/* Integer Rn or SP, alt. SVE position.  */
   AARCH64_OPND_SVE_SHLIMM_PRED,	  /* SVE shift left amount (predicated).  */
   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
+  AARCH64_OPND_SVE_SHLIMM_UNPRED_22,	/* SVE 3 bit shift left unpred.  */
   AARCH64_OPND_SVE_SHRIMM_PRED,	  /* SVE shift right amount (predicated).  */
   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,	/* SVE 3 bit shift right unpred.  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 3735fbc..c661c20 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -637,7 +637,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 168:
     case 169:
     case 170:
-    case 184:
     case 185:
     case 186:
     case 187:
@@ -646,8 +645,9 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 190:
     case 191:
     case 192:
-    case 198:
-    case 201:
+    case 193:
+    case 199:
+    case 202:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 13:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 203:
+    case 204:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -695,7 +695,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 81:
     case 158:
     case 160:
-    case 176:
     case 177:
     case 178:
     case 179:
@@ -703,6 +702,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 181:
     case 182:
     case 183:
+    case 184:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -840,21 +840,22 @@  aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_sve_scale (self, info, code, inst, errors);
     case 171:
     case 172:
-      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 173:
+      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 174:
     case 175:
+    case 176:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 193:
     case 194:
     case 195:
     case 196:
     case 197:
+    case 198:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 199:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 200:
-    case 202:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 201:
+    case 203:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a7281a9..d3f51ef 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20032,7 +20032,6 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 168:
     case 169:
     case 170:
-    case 184:
     case 185:
     case 186:
     case 187:
@@ -20041,8 +20040,9 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 190:
     case 191:
     case 192:
-    case 198:
-    case 201:
+    case 193:
+    case 199:
+    case 202:
       return aarch64_ext_regno (self, info, code, inst, errors);
     case 8:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20058,7 +20058,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 203:
+    case 204:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20095,7 +20095,6 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 81:
     case 158:
     case 160:
-    case 176:
     case 177:
     case 178:
     case 179:
@@ -20103,6 +20102,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 181:
     case 182:
     case 183:
+    case 184:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -20242,21 +20242,22 @@  aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_sve_scale (self, info, code, inst, errors);
     case 171:
     case 172:
-      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 173:
+      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 174:
     case 175:
+    case 176:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 193:
     case 194:
     case 195:
     case 196:
     case 197:
+    case 198:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-    case 199:
-      return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 200:
-    case 202:
+      return aarch64_ext_sve_index (self, info, code, inst, errors);
+    case 201:
+    case 203:
       return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 43d59ec..7de9ca7 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -197,6 +197,7 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-left immediate operand"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 292de34..6b43651 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2530,6 +2530,7 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 
 	case AARCH64_OPND_SVE_SHLIMM_PRED:
 	case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+	case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
 	  size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
 	  if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
 	    {
@@ -3355,6 +3356,7 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SIMM5:
     case AARCH64_OPND_SVE_SHLIMM_PRED:
     case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+    case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
     case AARCH64_OPND_SVE_SHRIMM_PRED:
     case AARCH64_OPND_SVE_SHRIMM_UNPRED:
     case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f6ab6ad..d7043a2 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4902,6 +4902,9 @@  struct aarch64_opcode aarch64_opcode_table[] =
       F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand")	\
     Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0,			\
       F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand")	\
+    Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED_22", 0,			\
+      F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3),			\
+      "a shift-left immediate operand")					\
     Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB,	\
       F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand")	\
     Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB,	\