[12/16,aarch64] New SVE_Zm4_11_INDEX operand.

Message ID 1556721866-21052-13-git-send-email-matthew.malcomson@arm.com
State New
Headers show
Series
  • SVE2 binutils instructions for aarch64
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Commit Message

Matthew Malcomson May 1, 2019, 2:44 p.m.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.

gas/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand.

include/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.

opcodes/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_Zm4_11_INDEX.
	(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
	(fields): Handle SVE_i2h field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
---
 gas/config/tc-aarch64.c  |  1 +
 include/opcode/aarch64.h |  1 +
 opcodes/aarch64-asm-2.c  | 13 +++++++------
 opcodes/aarch64-dis-2.c  | 13 +++++++------
 opcodes/aarch64-opc-2.c  |  1 +
 opcodes/aarch64-opc.c    |  3 +++
 opcodes/aarch64-opc.h    |  1 +
 opcodes/aarch64-tbl.h    |  3 +++
 8 files changed, 24 insertions(+), 12 deletions(-)

-- 
2.7.4

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d7fc372..fbe2dcf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5653,6 +5653,7 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_Zm3_INDEX:
 	case AARCH64_OPND_SVE_Zm3_22_INDEX:
 	case AARCH64_OPND_SVE_Zm3_11_INDEX:
+	case AARCH64_OPND_SVE_Zm4_11_INDEX:
 	case AARCH64_OPND_SVE_Zm4_INDEX:
 	case AARCH64_OPND_SVE_Zn_INDEX:
 	  reg_type = REG_TYPE_ZN;
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 285af27..99da95c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -412,6 +412,7 @@  enum aarch64_opnd
   AARCH64_OPND_SVE_Zm3_INDEX,	/* z0-z7[0-3] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
+  AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
   AARCH64_OPND_SVE_Zm4_INDEX,	/* z0-z15[0-1] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zn,		/* SVE vector register in Zn.  */
   AARCH64_OPND_SVE_Zn_INDEX,	/* Indexed SVE vector register, for DUP.  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index e6ddce7..3735fbc 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -646,8 +646,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 190:
     case 191:
     case 192:
-    case 197:
-    case 200:
+    case 198:
+    case 201:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 13:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 202:
+    case 203:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -849,11 +849,12 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 194:
     case 195:
     case 196:
+    case 197:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 198:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 199:
-    case 201:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 200:
+    case 202:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 6a802b4..a7281a9 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20041,8 +20041,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 190:
     case 191:
     case 192:
-    case 197:
-    case 200:
+    case 198:
+    case 201:
       return aarch64_ext_regno (self, info, code, inst, errors);
     case 8:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20058,7 +20058,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 202:
+    case 203:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20251,11 +20251,12 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 194:
     case 195:
     case 196:
+    case 197:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-    case 198:
-      return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 199:
-    case 201:
+      return aarch64_ext_sve_index (self, info, code, inst, errors);
+    case 200:
+    case 202:
       return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 256e696..43d59ec 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -220,6 +220,7 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
+  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5ee9e20..292de34 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -296,6 +296,7 @@  const aarch64_field fields[] =
     { 22,  1 }, /* SVE_i3h: high bit of 3-bit immediate.  */
     { 11,  1 }, /* SVE_i3l: low bit of 3-bit immediate.  */
     { 19,  2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19].  */
+    { 20,  1 }, /* SVE_i2h: high bit of 2bit immediate, bits.  */
     { 16,  3 }, /* SVE_imm3: 3-bit immediate field.  */
     { 16,  4 }, /* SVE_imm4: 4-bit immediate field.  */
     {  5,  5 }, /* SVE_imm5: 5-bit immediate field.  */
@@ -1519,6 +1520,7 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SVE_Zm3_INDEX:
 	case AARCH64_OPND_SVE_Zm3_22_INDEX:
 	case AARCH64_OPND_SVE_Zm3_11_INDEX:
+	case AARCH64_OPND_SVE_Zm4_11_INDEX:
 	case AARCH64_OPND_SVE_Zm4_INDEX:
 	  size = get_operand_fields_width (get_operand_from_code (type));
 	  shift = get_operand_specific_data (&aarch64_operands[type]);
@@ -3322,6 +3324,7 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SVE_Zm3_INDEX:
     case AARCH64_OPND_SVE_Zm3_22_INDEX:
     case AARCH64_OPND_SVE_Zm3_11_INDEX:
+    case AARCH64_OPND_SVE_Zm4_11_INDEX:
     case AARCH64_OPND_SVE_Zm4_INDEX:
     case AARCH64_OPND_SVE_Zn_INDEX:
       snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 8d18175..bb0a508 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -123,6 +123,7 @@  enum aarch64_field_kind
   FLD_SVE_i3h,
   FLD_SVE_i3l,
   FLD_SVE_i3h2,
+  FLD_SVE_i2h,
   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index c8ad71f..f6ab6ad 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4948,6 +4948,9 @@  struct aarch64_opcode aarch64_opcode_table[] =
     Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", 			\
       3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3),    \
       "an indexed SVE vector register")					\
+    Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", 			\
+      4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4),     \
+      "an indexed SVE vector register")					\
     Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", 			\
       4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16),				\
       "an indexed SVE vector register")					\