[10/16,aarch64] New SVE_SHRIMM_UNPRED_22 operand.

Message ID 1556721866-21052-11-git-send-email-matthew.malcomson@arm.com
State New
Headers show
Series
  • SVE2 binutils instructions for aarch64
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Commit Message

Matthew Malcomson May 1, 2019, 2:44 p.m.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.

Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.

The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.

gas/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
	operand.

include/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
	operand.
	(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.

opcodes/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-asm.c (aarch64_ins_sve_shrimm):
	(aarch64_encode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass decode.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_SHRIMM_UNPRED_22.
	(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
	operand.
---
 gas/config/tc-aarch64.c  |  1 +
 include/opcode/aarch64.h |  2 ++
 opcodes/aarch64-asm-2.c  | 19 ++++++++++---------
 opcodes/aarch64-asm.c    |  6 ++++--
 opcodes/aarch64-dis-2.c  | 19 ++++++++++---------
 opcodes/aarch64-dis.c    | 11 +++++++++++
 opcodes/aarch64-opc-2.c  |  5 +++--
 opcodes/aarch64-opc.c    | 18 ++++++++++++------
 opcodes/aarch64-tbl.h    |  7 +++++--
 9 files changed, 58 insertions(+), 30 deletions(-)

-- 
2.7.4

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f30b8df..d7fc372 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5784,6 +5784,7 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_SHLIMM_UNPRED:
 	case AARCH64_OPND_SVE_SHRIMM_PRED:
 	case AARCH64_OPND_SVE_SHRIMM_UNPRED:
+	case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
 	case AARCH64_OPND_SVE_SIMM5:
 	case AARCH64_OPND_SVE_SIMM5B:
 	case AARCH64_OPND_SVE_SIMM6:
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f46e378..ce9955d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -391,6 +391,7 @@  enum aarch64_opnd
   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
   AARCH64_OPND_SVE_SHRIMM_PRED,	  /* SVE shift right amount (predicated).  */
   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
+  AARCH64_OPND_SVE_SHRIMM_UNPRED_22,	/* SVE 3 bit shift right unpred.  */
   AARCH64_OPND_SVE_SIMM5,	/* SVE signed 5-bit immediate.  */
   AARCH64_OPND_SVE_SIMM5B,	/* SVE secondary signed 5-bit immediate.  */
   AARCH64_OPND_SVE_SIMM6,	/* SVE signed 6-bit immediate.  */
@@ -593,6 +594,7 @@  enum aarch64_insn_class
   sve_size_bh,
   sve_size_sd2,
   sve_size_013,
+  sve_shift_tsz_hsd,
   testbranch,
   cryptosm3,
   cryptosm4,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 0931c3f..e6ddce7 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -637,7 +637,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 168:
     case 169:
     case 170:
-    case 183:
     case 184:
     case 185:
     case 186:
@@ -646,8 +645,9 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 189:
     case 190:
     case 191:
-    case 196:
-    case 199:
+    case 192:
+    case 197:
+    case 200:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 13:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 201:
+    case 202:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -695,7 +695,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 81:
     case 158:
     case 160:
-    case 175:
     case 176:
     case 177:
     case 178:
@@ -703,6 +702,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 180:
     case 181:
     case 182:
+    case 183:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -843,16 +843,17 @@  aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 173:
     case 174:
+    case 175:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 192:
     case 193:
     case 194:
     case 195:
+    case 196:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 197:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 198:
-    case 200:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 199:
+    case 201:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 0ec27b2..6be17f9 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1241,8 +1241,9 @@  aarch64_ins_sve_shrimm (const aarch64_operand *self,
   const aarch64_opnd_info *prev_operand;
   unsigned int esize;
 
-  assert (info->idx > 0);
-  prev_operand = &inst->operands[info->idx - 1];
+  unsigned int opnd_backshift = get_operand_specific_data (self);
+  assert (info->idx >= (int)opnd_backshift);
+  prev_operand = &inst->operands[info->idx - opnd_backshift];
   esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
   insert_all_fields (self, code, 16 * esize - info->imm.value);
   return TRUE;
@@ -1624,6 +1625,7 @@  aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
     case sve_index:
     case sve_shift_pred:
     case sve_shift_unpred:
+    case sve_shift_tsz_hsd:
       /* For indices and shift amounts, the variant is encoded as
 	 part of the immediate.  */
       break;
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 62fd65a..6a802b4 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20032,7 +20032,6 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 168:
     case 169:
     case 170:
-    case 183:
     case 184:
     case 185:
     case 186:
@@ -20041,8 +20040,9 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 189:
     case 190:
     case 191:
-    case 196:
-    case 199:
+    case 192:
+    case 197:
+    case 200:
       return aarch64_ext_regno (self, info, code, inst, errors);
     case 8:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20058,7 +20058,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 201:
+    case 202:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20095,7 +20095,6 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 81:
     case 158:
     case 160:
-    case 175:
     case 176:
     case 177:
     case 178:
@@ -20103,6 +20102,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 180:
     case 181:
     case 182:
+    case 183:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -20245,16 +20245,17 @@  aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 173:
     case 174:
+    case 175:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 192:
     case 193:
     case 194:
     case 195:
+    case 196:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-    case 197:
-      return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 198:
-    case 200:
+      return aarch64_ext_sve_index (self, info, code, inst, errors);
+    case 199:
+    case 201:
       return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 1a727a4..5571ab6 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2832,6 +2832,17 @@  aarch64_decode_variant_using_iclass (aarch64_inst *inst)
 	variant = i;
       break;
 
+    case sve_shift_tsz_hsd:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
+      if (i == 0)
+	return FALSE;
+      while (i != 1)
+	{
+	  i >>= 1;
+	  variant += 1;
+	}
+      break;
+
     default:
       /* No mapping between instruction class and qualifiers.  */
       return TRUE;
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 56a77d6..256e696 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -197,8 +197,9 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
-  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
-  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 187ad12..5ee9e20 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2539,13 +2539,18 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 
 	case AARCH64_OPND_SVE_SHRIMM_PRED:
 	case AARCH64_OPND_SVE_SHRIMM_UNPRED:
-	  size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
-	  if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
+	case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
 	    {
-	      set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
-	      return 0;
-	    }
-	  break;
+	      unsigned int index =
+		(type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
+	      size = aarch64_get_qualifier_esize (opnds[idx - index].qualifier);
+	      if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
+		{
+		  set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
+		  return 0;
+		}
+	      break;
+	   }
 
 	default:
 	  break;
@@ -3349,6 +3354,7 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SVE_SHLIMM_UNPRED:
     case AARCH64_OPND_SVE_SHRIMM_PRED:
     case AARCH64_OPND_SVE_SHRIMM_UNPRED:
+    case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
     case AARCH64_OPND_SVE_SIMM5:
     case AARCH64_OPND_SVE_SIMM5B:
     case AARCH64_OPND_SVE_SIMM6:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0e20b66..c8ad71f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4902,10 +4902,13 @@  struct aarch64_opcode aarch64_opcode_table[] =
       F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand")	\
     Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0,			\
       F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand")	\
-    Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0,			\
+    Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB,	\
       F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand")	\
-    Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0,			\
+    Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB,	\
       F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand")	\
+    Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB,	\
+      F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3),			\
+      "a shift-right immediate operand")				\
     Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5),		\
       "a 5-bit signed immediate")					\
     Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b),	\