[06/16,aarch64] New SVE_ADDR_ZX operand.

Message ID 1556721866-21052-7-git-send-email-matthew.malcomson@arm.com
State New
Headers show
Series
  • SVE2 binutils instructions for aarch64
Related show

Commit Message

Matthew Malcomson May 1, 2019, 2:44 p.m.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.

gas/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
	(parse_address_main): Account for new addressing mode [Zn.S, Xm].
	(parse_operands): Handle new SVE_ADDR_ZX operand.

include/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.

opcodes/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_ADDR_ZX.
	(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
---
 gas/config/tc-aarch64.c  | 52 +++++++++++++++++++++++++++++++++++---
 include/opcode/aarch64.h |  1 +
 opcodes/aarch64-asm-2.c  | 65 ++++++++++++++++++++++++------------------------
 opcodes/aarch64-dis-2.c  | 65 ++++++++++++++++++++++++------------------------
 opcodes/aarch64-opc-2.c  |  1 +
 opcodes/aarch64-opc.c    | 18 ++++++++++++++
 opcodes/aarch64-tbl.h    |  3 +++
 7 files changed, 137 insertions(+), 68 deletions(-)

-- 
2.7.4

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 612febd..f30b8df 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -449,6 +449,7 @@  get_reg_expected_msg (aarch64_reg_type reg_type)
 
 /* Some well known registers that we refer to directly elsewhere.  */
 #define REG_SP	31
+#define REG_ZR	31
 
 /* Instructions take 4 bytes in the object file.  */
 #define INSN_SIZE	4
@@ -3393,6 +3394,7 @@  parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
      [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
      [Zn.S,#imm]
      [Zn.D,#imm]
+     [Zn.S{, Xm}]
      [Zn.S,Zm.S{,LSL #imm}]      // in ADR
      [Zn.D,Zm.D{,LSL #imm}]      // in ADR
      [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
@@ -3558,6 +3560,7 @@  parse_address_main (char **str, aarch64_opnd_info *operand,
 		return FALSE;
 	    }
 	  /* We only accept:
+	     [base,Xm]  # For vector plus scalar SVE2 indexing.
 	     [base,Xm{,LSL #imm}]
 	     [base,Xm,SXTX {#imm}]
 	     [base,Wm,(S|U)XTW {#imm}]  */
@@ -3571,7 +3574,10 @@  parse_address_main (char **str, aarch64_opnd_info *operand,
 		  return FALSE;
 		}
 	      if (aarch64_get_qualifier_esize (*base_qualifier)
-		  != aarch64_get_qualifier_esize (*offset_qualifier))
+		  != aarch64_get_qualifier_esize (*offset_qualifier)
+		  && (operand->type != AARCH64_OPND_SVE_ADDR_ZX
+		      || *base_qualifier != AARCH64_OPND_QLF_S_S
+		      || *offset_qualifier != AARCH64_OPND_QLF_X))
 		{
 		  set_syntax_error (_("offset has different size from base"));
 		  return FALSE;
@@ -3689,7 +3695,9 @@  parse_address_main (char **str, aarch64_opnd_info *operand,
     }
 
   /* If at this point neither .preind nor .postind is set, we have a
-     bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0].  */
+     bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0].
+     For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
+     [Zn.<T>, xzr].  */
   if (operand->addr.preind == 0 && operand->addr.postind == 0)
     {
       if (operand->addr.writeback)
@@ -3700,8 +3708,17 @@  parse_address_main (char **str, aarch64_opnd_info *operand,
 	}
 
       operand->addr.preind = 1;
-      inst.reloc.exp.X_op = O_constant;
-      inst.reloc.exp.X_add_number = 0;
+      if (operand->type == AARCH64_OPND_SVE_ADDR_ZX)
+	{
+	  operand->addr.offset.is_reg = 1;
+	  operand->addr.offset.regno = REG_ZR;
+	  *offset_qualifier = AARCH64_OPND_QLF_X;
+	}
+      else
+	{
+	  inst.reloc.exp.X_op = O_constant;
+	  inst.reloc.exp.X_add_number = 0;
+	}
     }
 
   *str = p;
@@ -6416,6 +6433,33 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	  info->qualifier = offset_qualifier;
 	  goto regoff_addr;
 
+	case AARCH64_OPND_SVE_ADDR_ZX:
+	  /* [Zn.<T>{, <Xm>}].  */
+	  po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
+					      &offset_qualifier));
+	  /* Things to check:
+	      base_qualifier either S_S or S_D
+	      offset_qualifier must be X
+	      */
+	  if ((base_qualifier != AARCH64_OPND_QLF_S_S
+	       && base_qualifier != AARCH64_OPND_QLF_S_D)
+	      || offset_qualifier != AARCH64_OPND_QLF_X)
+	    {
+	      set_syntax_error (_("invalid addressing mode"));
+	      goto failure;
+	    }
+	  info->qualifier = base_qualifier;
+	  if (!info->addr.offset.is_reg || info->addr.pcrel
+	      || !info->addr.preind || info->addr.writeback
+	      || info->shifter.operator_present != 0)
+	    {
+	      set_syntax_error (_("invalid addressing mode"));
+	      goto failure;
+	    }
+	  info->shifter.kind = AARCH64_MOD_LSL;
+	  break;
+
+
 	case AARCH64_OPND_SVE_ADDR_ZI_U5:
 	case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
 	case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 1c3f126..5e8f6dd 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -334,6 +334,7 @@  enum aarch64_opnd
   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
+  AARCH64_OPND_SVE_ADDR_ZX,	    /* SVE [Zn.<T>{, <Xm>}].  */
   AARCH64_OPND_SVE_ADDR_RZ,	    /* SVE [<Xn|SP>, Zm.D].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 0b67ceb..0931c3f 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -627,7 +627,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 27:
     case 28:
     case 29:
-    case 160:
     case 161:
     case 162:
     case 163:
@@ -637,7 +636,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 167:
     case 168:
     case 169:
-    case 182:
+    case 170:
     case 183:
     case 184:
     case 185:
@@ -646,8 +645,9 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 188:
     case 189:
     case 190:
-    case 195:
-    case 198:
+    case 191:
+    case 196:
+    case 199:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 13:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -659,7 +659,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 200:
+    case 201:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -693,9 +693,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 79:
     case 80:
     case 81:
-    case 157:
-    case 159:
-    case 174:
+    case 158:
+    case 160:
     case 175:
     case 176:
     case 177:
@@ -703,6 +702,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 179:
     case 180:
     case 181:
+    case 182:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -712,10 +712,10 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 46:
       return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
     case 50:
-    case 147:
+    case 148:
       return aarch64_ins_fpimm (self, info, code, inst, errors);
     case 67:
-    case 155:
+    case 156:
       return aarch64_ins_limm (self, info, code, inst, errors);
     case 68:
       return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -725,11 +725,11 @@  aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_fbits (self, info, code, inst, errors);
     case 72:
     case 73:
-    case 152:
+    case 153:
       return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 74:
-    case 151:
-    case 153:
+    case 152:
+    case 154:
       return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
     case 75:
     case 76:
@@ -800,8 +800,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 127:
     case 128:
     case 129:
-      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 130:
+      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 131:
     case 132:
     case 133:
@@ -809,49 +809,50 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 135:
     case 136:
     case 137:
-      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 138:
+      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 139:
     case 140:
     case 141:
-      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 142:
-      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 143:
-      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 144:
-      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 145:
-      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 146:
+      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+    case 147:
       return aarch64_ins_sve_asimm (self, info, code, inst, errors);
-    case 148:
-      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 149:
-      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 150:
+      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+    case 151:
       return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
-    case 154:
+    case 155:
       return aarch64_ins_inv_limm (self, info, code, inst, errors);
-    case 156:
+    case 157:
       return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
-    case 158:
+    case 159:
       return aarch64_ins_sve_scale (self, info, code, inst, errors);
-    case 170:
     case 171:
-      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 172:
+      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 173:
+    case 174:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 191:
     case 192:
     case 193:
     case 194:
+    case 195:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 196:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 197:
-    case 199:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 198:
+    case 200:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 630ef20..62fd65a 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20022,7 +20022,6 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 27:
     case 28:
     case 29:
-    case 160:
     case 161:
     case 162:
     case 163:
@@ -20032,7 +20031,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 167:
     case 168:
     case 169:
-    case 182:
+    case 170:
     case 183:
     case 184:
     case 185:
@@ -20041,8 +20040,9 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 188:
     case 189:
     case 190:
-    case 195:
-    case 198:
+    case 191:
+    case 196:
+    case 199:
       return aarch64_ext_regno (self, info, code, inst, errors);
     case 8:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20058,7 +20058,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 200:
+    case 201:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20093,9 +20093,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 79:
     case 80:
     case 81:
-    case 157:
-    case 159:
-    case 174:
+    case 158:
+    case 160:
     case 175:
     case 176:
     case 177:
@@ -20103,6 +20102,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 179:
     case 180:
     case 181:
+    case 182:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -20114,10 +20114,10 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 47:
       return aarch64_ext_shll_imm (self, info, code, inst, errors);
     case 50:
-    case 147:
+    case 148:
       return aarch64_ext_fpimm (self, info, code, inst, errors);
     case 67:
-    case 155:
+    case 156:
       return aarch64_ext_limm (self, info, code, inst, errors);
     case 68:
       return aarch64_ext_aimm (self, info, code, inst, errors);
@@ -20127,11 +20127,11 @@  aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_fbits (self, info, code, inst, errors);
     case 72:
     case 73:
-    case 152:
+    case 153:
       return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
     case 74:
-    case 151:
-    case 153:
+    case 152:
+    case 154:
       return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
     case 75:
     case 76:
@@ -20202,8 +20202,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 127:
     case 128:
     case 129:
-      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 130:
+      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 131:
     case 132:
     case 133:
@@ -20211,49 +20211,50 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 135:
     case 136:
     case 137:
-      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 138:
+      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 139:
     case 140:
     case 141:
-      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 142:
-      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 143:
-      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 144:
-      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 145:
-      return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 146:
+      return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+    case 147:
       return aarch64_ext_sve_asimm (self, info, code, inst, errors);
-    case 148:
-      return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
     case 149:
-      return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
     case 150:
+      return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+    case 151:
       return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
-    case 154:
+    case 155:
       return aarch64_ext_inv_limm (self, info, code, inst, errors);
-    case 156:
+    case 157:
       return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
-    case 158:
+    case 159:
       return aarch64_ext_sve_scale (self, info, code, inst, errors);
-    case 170:
     case 171:
-      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 172:
+      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 173:
+    case 174:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 191:
     case 192:
     case 193:
     case 194:
+    case 195:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-    case 196:
-      return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 197:
-    case 199:
+      return aarch64_ext_sve_index (self, info, code, inst, errors);
+    case 198:
+    case 200:
       return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index db2fc37..56a77d6 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -150,6 +150,7 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_Rm}, "vector of address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 695146f..f76715f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1899,6 +1899,17 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	  max_value = 7;
 	  goto sve_imm_offset;
 
+	case AARCH64_OPND_SVE_ADDR_ZX:
+	  /* Everything is already ensured by parse_operands or
+	     aarch64_ext_sve_addr_rr_lsl (because this is a very specific
+	     argument type).  */
+	  assert (opnd->addr.offset.is_reg);
+	  assert (opnd->addr.preind);
+	  assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
+	  assert (opnd->shifter.kind == AARCH64_MOD_LSL);
+	  assert (opnd->shifter.operator_present == 0);
+	  break;
+
 	case AARCH64_OPND_SVE_ADDR_R:
 	case AARCH64_OPND_SVE_ADDR_RR:
 	case AARCH64_OPND_SVE_ADDR_RR_LSL1:
@@ -3580,6 +3591,13 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 	 get_offset_int_reg_name (opnd));
       break;
 
+    case AARCH64_OPND_SVE_ADDR_ZX:
+      print_register_offset_address
+	(buf, size, opnd,
+	 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
+	 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
+      break;
+
     case AARCH64_OPND_SVE_ADDR_RZ:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 826b4df..0e20b66 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4786,6 +4786,9 @@  struct aarch64_opcode aarch64_opcode_table[] =
     Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3",			\
       (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm),		\
       "an address with a scalar register offset")			\
+    Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX",				\
+      0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm),				\
+      "vector of address with a scalar register offset")		\
     Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB,	\
       F(FLD_Rn,FLD_SVE_Zm_16),						\
       "an address with a vector register offset")			\