[GAS,Arm] CLI with architecture sensitive extensions

Message ID 3a366216-57d9-d698-d82b-55d5bdff94ad@arm.com
State New
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  • [GAS,Arm] CLI with architecture sensitive extensions
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Commit Message

Andre Vieira (lists) March 22, 2019, 10:34 a.m.
Hi,

This patch adds a new framework to add architecture sensitive 
extensions, like GCC does.
This patch also implements all architecture extensions currently 
available in GCC.

This framework works as follows.  To enable architecture sensitive 
extensions for a particular architecture, that architecture must contain 
an ARM_ARCH_OPT2 entry in the 'arm_archs' table.
All fields here are the same as previous, with the addition of a new 
extra field at the end to <name> it's extension table.  This <name>, 
corresponds to a <name>_ext_table of type 'struct arm_ext_table'.  This 
struct can be filled with three types of entries:
ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means 
+<ext> will enable <enable_bits>
ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means 
+no<ext> will disable <disable_bits>
ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set 
<disable_bits>), which means +<ext> will enable <enable_bits> and 
+no<ext> will disable <disable_bits> (this is to be used instead of 
adding an ARM_ADD and ARM_REMOVE for the same <ext>)

This patch does not disable the use of the old extensions, even if some 
of them are duplicated in the new tables.  This is a "in-between-step" 
as we may want to deprecate the old table of extensions in later 
patches.  For now, GAS will first look for the +<ext> or +no<ext> in the 
new table and if no entry is found it will continue searching in the old 
table, following old behaviour.  If only an ARM_ADD or an ARM_REMOVE is 
defined for <ext> and +no<ext> or +<ext> resp. is used then it also 
continues to search the old table for it.

A couple of caveats:
- This patch does not enable the use of these architecture extensions 
with the
'.arch_extension' directive.  This is future work that I will tend to later.
- This patch does not enable the use of these architecture extensions 
with the
-mcpu option.  This is future work that I will tend to later.
- This patch does not change the current behaviour when combining an
architecture extension and using -mfpu on the command-line.  The current
behaviour of GAS is to stage the union of feature bits enabled by both 
-march
and -mfpu.  GCC behaves differently here, so this is something we may 
want to
revisit on a later date.

For testing I duplicated an attributes test prior to Armv8-A for every 
set of enabled bits by one of the new extensions, I didn't test all 
possible new -march +ext combinations as that would be too much I 
believe.  For armv8-a I reused a couple of instruction tests using the 
new extensions. For Armv8-m I added two new tests.

Cheers,
Andre

gas/ChangeLog:
2019-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * config/tc-arm.c (arm_ext_table): New struct type.
         (arm_arch_option_table): Add new 'arm_ext_table' field.
         (ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.
         (armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,
          armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,
          armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,
          armv85a_ext_table, armv8m_main_ext_table,
          armv8r_ext_table): New architecture extension tables.
         (ARM_ARCH_OPT): Add new default field.
         (ARM_ARCH_OPT2): New macro.
         (arm_archs): Extend some architectures with the new architecture
         extension tables mentioned above.
         (arm_extensions): Add DEPRECATED comment with instructions to 
use new
         table.
         (arm_parse_extension): Change to use new extension tables.
         (arm_parse_cpu): Don't change existing behavior.
         (arm_parse_arch): Change to use new extension tables.
         * doc/c-arm.texi: Document new architecture extensions.
         * testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new
         extension option rather than -mfpu and change expected behaviour to
         sane outputs.
         * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.
         * testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.
         * testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.
         * testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.
         * testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.
         * testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.
         * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.
         * testsuite/gas/arm/armv8_2+rdma-ext.d: New.
         * testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.
         * testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.
         * testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.
         * testsuite/gas/arm/armv8_3-a-fp-ext.d: New.
         * testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.
         * testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.
         * testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.
         * testsuite/gas/arm/armv8m.main+fp.d: New.
         * testsuite/gas/arm/armv8m.main+fp.dp.d: New.
         * testsuite/gas/arm/attr-ext-fpv5-d16.d: New.
         * testsuite/gas/arm/attr-ext-fpv5.d: New.
         * testsuite/gas/arm/attr-ext-idiv.d: New.
         * testsuite/gas/arm/attr-ext-mp.d: New.
         * testsuite/gas/arm/attr-ext-neon-fp16.d: New.
         * testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.
         * testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.
         * testsuite/gas/arm/attr-ext-sec.d: New.
         * testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.
         * testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.
         * testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.
         * testsuite/gas/arm/attr-ext-vfpv3.d: New.
         * testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.
         * testsuite/gas/arm/attr-ext-vfpv3xd.d: New.
         * testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.
         * testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.
         * testsuite/gas/arm/attr-ext-vfpv4.d: New.
         * testsuite/gas/arm/dotprod-mandatory-ext.d: New.
         * testsuite/gas/arm/fpv5-d16.s: New.
         * testsuite/gas/arm/fpv5-sp-d16.s: New.

include/ChangeLog:
2019-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * opcode/arm.h (FPU_NEON_ARMV8_1): New.
         (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
         (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
         (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
         (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
         (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
         (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
         (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.

Comments

Andre Vieira (lists) March 22, 2019, 1:23 p.m. | #1
Here is the same patch with some minor comment changes after someone 
pointed them out to me.

Cheers,
Andre

On 22/03/2019 10:34, Andre Vieira (lists) wrote:
> Hi,

> 

> This patch adds a new framework to add architecture sensitive 

> extensions, like GCC does.

> This patch also implements all architecture extensions currently 

> available in GCC.

> 

> This framework works as follows.  To enable architecture sensitive 

> extensions for a particular architecture, that architecture must contain 

> an ARM_ARCH_OPT2 entry in the 'arm_archs' table.

> All fields here are the same as previous, with the addition of a new 

> extra field at the end to <name> it's extension table.  This <name>, 

> corresponds to a <name>_ext_table of type 'struct arm_ext_table'.  This 

> struct can be filled with three types of entries:

> ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means 

> +<ext> will enable <enable_bits>

> ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means 

> +no<ext> will disable <disable_bits>

> ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set 

> <disable_bits>), which means +<ext> will enable <enable_bits> and 

> +no<ext> will disable <disable_bits> (this is to be used instead of 

> adding an ARM_ADD and ARM_REMOVE for the same <ext>)

> 

> This patch does not disable the use of the old extensions, even if some 

> of them are duplicated in the new tables.  This is a "in-between-step" 

> as we may want to deprecate the old table of extensions in later 

> patches.  For now, GAS will first look for the +<ext> or +no<ext> in the 

> new table and if no entry is found it will continue searching in the old 

> table, following old behaviour.  If only an ARM_ADD or an ARM_REMOVE is 

> defined for <ext> and +no<ext> or +<ext> resp. is used then it also 

> continues to search the old table for it.

> 

> A couple of caveats:

> - This patch does not enable the use of these architecture extensions 

> with the

> '.arch_extension' directive.  This is future work that I will tend to 

> later.

> - This patch does not enable the use of these architecture extensions 

> with the

> -mcpu option.  This is future work that I will tend to later.

> - This patch does not change the current behaviour when combining an

> architecture extension and using -mfpu on the command-line.  The current

> behaviour of GAS is to stage the union of feature bits enabled by both 

> -march

> and -mfpu.  GCC behaves differently here, so this is something we may 

> want to

> revisit on a later date.

> 

> For testing I duplicated an attributes test prior to Armv8-A for every 

> set of enabled bits by one of the new extensions, I didn't test all 

> possible new -march +ext combinations as that would be too much I 

> believe.  For armv8-a I reused a couple of instruction tests using the 

> new extensions. For Armv8-m I added two new tests.

> 

> Cheers,

> Andre

> 

> gas/ChangeLog:

> 2019-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>          * config/tc-arm.c (arm_ext_table): New struct type.

>          (arm_arch_option_table): Add new 'arm_ext_table' field.

>          (ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.

>          (armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,

>           armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,

>           armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,

>           armv85a_ext_table, armv8m_main_ext_table,

>           armv8r_ext_table): New architecture extension tables.

>          (ARM_ARCH_OPT): Add new default field.

>          (ARM_ARCH_OPT2): New macro.

>          (arm_archs): Extend some architectures with the new architecture

>          extension tables mentioned above.

>          (arm_extensions): Add DEPRECATED comment with instructions to 

> use new

>          table.

>          (arm_parse_extension): Change to use new extension tables.

>          (arm_parse_cpu): Don't change existing behavior.

>          (arm_parse_arch): Change to use new extension tables.

>          * doc/c-arm.texi: Document new architecture extensions.

>          * testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new

>          extension option rather than -mfpu and change expected 

> behaviour to

>          sane outputs.

>          * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.

>          * testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.

>          * testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.

>          * testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.

>          * testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.

>          * testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.

>          * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.

>          * testsuite/gas/arm/armv8_2+rdma-ext.d: New.

>          * testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.

>          * testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.

>          * testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.

>          * testsuite/gas/arm/armv8_3-a-fp-ext.d: New.

>          * testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.

>          * testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.

>          * testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.

>          * testsuite/gas/arm/armv8m.main+fp.d: New.

>          * testsuite/gas/arm/armv8m.main+fp.dp.d: New.

>          * testsuite/gas/arm/attr-ext-fpv5-d16.d: New.

>          * testsuite/gas/arm/attr-ext-fpv5.d: New.

>          * testsuite/gas/arm/attr-ext-idiv.d: New.

>          * testsuite/gas/arm/attr-ext-mp.d: New.

>          * testsuite/gas/arm/attr-ext-neon-fp16.d: New.

>          * testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.

>          * testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.

>          * testsuite/gas/arm/attr-ext-sec.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv3.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv3xd.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.

>          * testsuite/gas/arm/attr-ext-vfpv4.d: New.

>          * testsuite/gas/arm/dotprod-mandatory-ext.d: New.

>          * testsuite/gas/arm/fpv5-d16.s: New.

>          * testsuite/gas/arm/fpv5-sp-d16.s: New.

> 

> include/ChangeLog:

> 2019-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>          * opcode/arm.h (FPU_NEON_ARMV8_1): New.

>          (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.

>          (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.

>          (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.

>          (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.

>          (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.

>          (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.

>          (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5bcd88ba8feb06177a5a909d4405b59861677e21..4218d059d6d4cbe922c4eb8215afaee5d39c18e3 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -26308,17 +26308,217 @@ static const struct arm_cpu_option_table arm_cpus[] =
 };
 #undef ARM_CPU_OPT
 
+struct arm_ext_table
+{
+  const char *		  name;
+  size_t		  name_len;
+  const arm_feature_set	  merge;
+  const arm_feature_set	  clear;
+};
+
 struct arm_arch_option_table
 {
-  const char *           name;
-  size_t                 name_len;
-  const arm_feature_set	 value;
-  const arm_feature_set	 default_fpu;
+  const char *			name;
+  size_t			name_len;
+  const arm_feature_set		value;
+  const arm_feature_set		default_fpu;
+  const struct arm_ext_table *	ext_table;
+};
+
+/* Used to add support for +E and +noE extension.  */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension.  */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension.  */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+			    ~0 & ~FPU_ENDIAN_PURE)
+
+static const struct arm_ext_table armv5te_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7ve_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
+  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
+  ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
+  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
+  ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
+  ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),  /* Alias for +fp.  */
+  ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
+
+  ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
+	   ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
+
+  /* Aliases for +simd.  */
+  ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
+
+  ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+  ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+  ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
+
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7a_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
+  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp.  */
+  ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
+  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
+  ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
+  ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
+  ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
+
+  ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
+	   ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
+
+  /* Aliases for +simd.  */
+  ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+  ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+
+  ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
+  ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
+
+  ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
+  ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7r_ext_table[] =
+{
+  ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
+  ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp.  */
+  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
+  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp.  */
+  ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
+  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
+  ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
+	   ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7em_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
+  /* Alias for +fp, used to be known as fpv4-sp-d16.  */
+  ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
+  ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
+  ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
+  ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv8a_ext_table[] =
+{
+  ARM_ADD ("crc", ARCH_CRC_ARMV8),
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation without SIMD, so the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+
+static const struct arm_ext_table armv81a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation without SIMD, so the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv82a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
+  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
+  ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+  ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
+
+  /* Armv8-a does not allow an FP implementation without SIMD, so the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv84a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
+  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation without SIMD, so the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv85a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
+  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation without SIMD, so the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv8m_main_ext_table[] =
+{
+  ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+		  ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
+  ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
+  ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv8r_ext_table[] =
+{
+  ARM_ADD ("crc", ARCH_CRC_ARMV8),
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
 /* This list should, at a minimum, contain all the architecture names
    recognized by GCC.  */
-#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
+#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
+#define ARM_ARCH_OPT2(N, V, DF, ext) \
+  { N, sizeof (N) - 1, V, DF, ext##_ext_table }
 
 static const struct arm_arch_option_table arm_archs[] =
 {
@@ -26336,50 +26536,51 @@ static const struct arm_arch_option_table arm_archs[] =
   ARM_ARCH_OPT ("armv5",	  ARM_ARCH_V5,		FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv5t",	  ARM_ARCH_V5T,		FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv5txm",	  ARM_ARCH_V5TxM,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_VFP, armv5te),
+  ARM_ARCH_OPT2 ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_VFP,	armv5te),
   /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
      kept to preserve existing behaviour.  */
-  ARM_ARCH_OPT ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_VFP,	armv5te),
   /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
      kept to preserve existing behaviour.  */
-  ARM_ARCH_OPT ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
   ARM_ARCH_OPT ("armv6-m",	  ARM_ARCH_V6M,		FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6s-m",	  ARM_ARCH_V6SM,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_VFP, armv7),
   /* The official spelling of the ARMv7 profile variants is the dashed form.
      Accept the non-dashed form for compatibility with old toolchains.  */
-  ARM_ARCH_OPT ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
+  ARM_ARCH_OPT2 ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_VFP, armv7ve),
+  ARM_ARCH_OPT2 ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
   ARM_ARCH_OPT ("armv7m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
+  ARM_ARCH_OPT2 ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
   ARM_ARCH_OPT ("armv7-m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_VFP, armv7em),
   ARM_ARCH_OPT ("armv8-m.base",	  ARM_ARCH_V8M_BASE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8-m.main",	  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv8-m.main",  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP,
+		 armv8m_main),
+  ARM_ARCH_OPT2 ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP, armv8a),
+  ARM_ARCH_OPT2 ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP, armv81a),
+  ARM_ARCH_OPT2 ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP, armv82a),
+  ARM_ARCH_OPT2 ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_VFP, armv82a),
+  ARM_ARCH_OPT2 ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_VFP, armv8r),
+  ARM_ARCH_OPT2 ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_VFP, armv84a),
+  ARM_ARCH_OPT2 ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_VFP, armv85a),
   ARM_ARCH_OPT ("xscale",	  ARM_ARCH_XSCALE,	FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt",	  ARM_ARCH_IWMMXT,	FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt2",	  ARM_ARCH_IWMMXT2,	FPU_ARCH_VFP),
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
 };
 #undef ARM_ARCH_OPT
 
@@ -26402,6 +26603,8 @@ struct arm_option_extension_value_table
 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
 
+/* DEPRECATED: Refrain from using this table to add any new extensions, instead
+   use the context sensitive approach using arm_ext_table's.  */
 static const struct arm_option_extension_value_table arm_extensions[] =
 {
   ARM_EXT_OPT ("crc",  ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
@@ -26574,7 +26777,8 @@ struct arm_long_option_table
 
 static bfd_boolean
 arm_parse_extension (const char *str, const arm_feature_set *opt_set,
-		     arm_feature_set *ext_set)
+		     arm_feature_set *ext_set,
+		     const struct arm_ext_table *ext_table)
 {
   /* We insist on extensions being specified in alphabetical order, and with
      extensions being added before being removed.  We achieve this by having
@@ -26640,6 +26844,41 @@ arm_parse_extension (const char *str, const arm_feature_set *opt_set,
       gas_assert (adding_value != -1);
       gas_assert (opt != NULL);
 
+      if (ext_table != NULL)
+	{
+	  const struct arm_ext_table * ext_opt = ext_table;
+	  bfd_boolean found = FALSE;
+	  for (; ext_opt->name != NULL; ext_opt++)
+	    if (ext_opt->name_len == len
+		&& strncmp (ext_opt->name, str, len) == 0)
+	      {
+		if (adding_value)
+		  {
+		    if (ARM_FEATURE_ZERO (ext_opt->merge))
+			/* TODO: Option not supported.  When we remove the
+			   legacy table this case should error out.  */
+			continue;
+
+		    ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
+		  }
+		else
+		  {
+		    if (ARM_FEATURE_ZERO (ext_opt->clear))
+			/* TODO: Option not supported.  When we remove the
+			   legacy table this case should error out.  */
+			continue;
+		    ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
+		  }
+		found = TRUE;
+		break;
+	      }
+	  if (found)
+	    {
+	      str = ext;
+	      continue;
+	    }
+	}
+
       /* Scan over the options table trying to find an exact match. */
       for (; opt->name != NULL; opt++)
 	if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
@@ -26748,7 +26987,7 @@ arm_parse_cpu (const char *str)
 	  }
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt);
+	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
 
 	return TRUE;
       }
@@ -26786,7 +27025,8 @@ arm_parse_arch (const char *str)
 	strcpy (selected_cpu_name, opt->name);
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, march_cpu_opt, march_ext_opt);
+	  return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
+				      opt->ext_table);
 
 	return TRUE;
       }
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 4fb6cadf93526be4736e38cfcac27aa457df40c9..184d7160a887d3512de50255c17bcbb1ba661667 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -248,7 +248,9 @@ names are recognized:
 @code{armv8-r},
 @code{armv8.4-a},
 @code{armv8.5-a},
-@code{iwmmxt}
+@code{armv8-m.base},
+@code{armv8-m.main},
+@code{iwmmxt},
 @code{iwmmxt2}
 and
 @code{xscale}.
@@ -256,8 +258,167 @@ If both @code{-mcpu} and
 @code{-march} are specified, the assembler will use
 the setting for @code{-mcpu}.
 
-The architecture option can be extended with the same instruction set
-extension options as the @code{-mcpu} option.
+The architecture option can be extended with a set extension options.  These
+extensions are context sensitive, i.e. the same extension may mean different
+things when used with different architectures.  When used together with a
+@code{-mfpu} option, the union of both feature enablement is taken.
+See their availability and meaning below:
+
+For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
+
+@code{+fp}: Enables VFPv2 instructions.
+@code{+nofp}: Disables all FPU instrunctions.
+
+For @code{armv7}:
+
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv7-a}:
+
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3-d16}: Alias for @code{+fp}.
+@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
+conversion instructions and 16 double-word registers.
+@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
+instructions and 32 double-word registers.
+@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
+@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
+@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
+registers.
+@code{+neon}: Alias for @code{+simd}.
+@code{+neon-vfpv3}: Alias for @code{+simd}.
+@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
+NEONv1 instructions with 32 double-word registers.
+@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
+double-word registers.
+@code{+mp}: Enables Multiprocessing Extensions.
+@code{+sec}: Enables Security Extensions.
+@code{+nofp}: Disables all FPU and NEON instructions.
+@code{+nosimd}: Disables all NEON instructions.
+
+For @code{armv7ve}:
+
+@code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
+@code{+vfpv4-d16}: Alias for @code{+fp}.
+@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
+conversion instructions and 16 double-word registers.
+@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
+instructions and 32 double-word registers.
+@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
+@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
+double-word registers.
+@code{+neon-vfpv4}: Alias for @code{+simd}.
+@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
+registers.
+@code{+neon-vfpv3}: Alias for @code{+neon}.
+@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
+NEONv1 instructions with 32 double-word registers.
+double-word registers.
+@code{+nofp}: Disables all FPU and NEON instructions.
+@code{+nosimd}: Disables all NEON instructions.
+
+For @code{armv7-r}:
+
+@code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
+double-word registers.
+@code{+vfpv3xd}: Alias for @code{+fp.sp}.
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3-d16}: Alias for @code{+fp}.
+@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
+floating-point conversion instructions with 16 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
+conversion instructions with 16 double-word registers.
+@code{+idiv}: Enables integer division instructions in ARM mode.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv7e-m}:
+
+@code{+fp}: Enables single-precision only VFPv4 instructions with 16
+double-word registers.
+@code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
+@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
+double-word registers.
+@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+fpv5-d16"}: Alias for @code{+fp.dp}.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv8-m.main}:
+
+@code{+dsp}: Enables DSP Extension.
+@code{+fp}: Enables single-precision only VFPv5 instructions with 16
+double-word registers.
+@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+nofp}: Disables all FPU instructions.
+@code{+nodsp}: Disables DSP Extension.
+
+For @code{armv8-a}:
+
+@code{+crc}: Enables CRC32 Extension.
+@code{+simd}: Enables VFP and NEON for Armv8-A.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.1-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.2-a} and @code{armv8.3-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A.
+@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
+@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
+for Armv8.2-A, implies @code{+fp16}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.4-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
+Armv8.2-A.
+@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
+Variant Extensions for Armv8.2-A, implies @code{+simd}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocryptp}: Disables Cryptography Extensions.
+
+For @code{armv8.5-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
+Armv8.2-A.
+@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
+Variant Extensions for Armv8.2-A, implies @code{+simd}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocryptp}: Disables Cryptography Extensions.
+
 
 @cindex @code{-mfpu=} command-line option, ARM
 @item -mfpu=@var{floating-point-format}
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..b98e7cf7b24806b77d70cc56d5f4a6bef040394a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d
@@ -0,0 +1,4 @@
+#name: Invalid armv8.2-a scalar fp16
+#source: armv8-2-fp16-scalar-bad.s
+#as: -march=armv8.2-a+fp16
+#error_output: armv8-2-fp16-scalar-bad.l
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..0b5e4e4861c6522e4cc24d63051fad3e9c145939
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
@@ -0,0 +1,75 @@
+#name: ARM v8.2 FP16 support on scalar
+#source: armv8-2-fp16-scalar.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+Disassembly of section .text:
+
+00000000 <label-0xc>:
+   0:	ee001910 	vmov.f16	s0, r1
+   4:	ee100990 	vmov.f16	r0, s1
+   8:	eeb00900 	vmov.f16	s0, #0	; 0x40000000  2.0
+
+0000000c <label>:
+   c:	00000ffe 	.word	0x00000ffe
+  10:	ed5f1906 	vldr.16	s3, \[pc, #-12\]	; c <label>
+  14:	ed1f3902 	vldr.16	s6, \[pc, #-4\]	; 18 <label\+0xc>
+  18:	eddf1902 	vldr.16	s3, \[pc, #4\]	; 24 <label\+0x18>
+  1c:	edd00902 	vldr.16	s1, \[r0, #4\]
+  20:	ed101902 	vldr.16	s2, \[r0, #-4\]
+  24:	ed803902 	vstr.16	s6, \[r0, #4\]
+  28:	ed405902 	vstr.16	s11, \[r0, #-4\]
+  2c:	eec6298c 	vdiv.f16	s5, s13, s24
+  30:	eee6298c 	vfma.f16	s5, s13, s24
+  34:	eee629cc 	vfms.f16	s5, s13, s24
+  38:	eed629cc 	vfnma.f16	s5, s13, s24
+  3c:	eed6298c 	vfnms.f16	s5, s13, s24
+  40:	fec6298c 	vmaxnm.f16	s5, s13, s24
+  44:	fec629cc 	vminnm.f16	s5, s13, s24
+  48:	ee46298c 	vmla.f16	s5, s13, s24
+  4c:	ee4629cc 	vmls.f16	s5, s13, s24
+  50:	ee66298c 	vmul.f16	s5, s13, s24
+  54:	ee5629cc 	vnmla.f16	s5, s13, s24
+  58:	ee56298c 	vnmls.f16	s5, s13, s24
+  5c:	ee6629cc 	vnmul.f16	s5, s13, s24
+  60:	ee7629cc 	vsub.f16	s5, s13, s24
+  64:	eef029c6 	vabs.f16	s5, s12
+  68:	ee722986 	vadd.f16	s5, s5, s12
+  6c:	eef129c6 	vsqrt.f16	s5, s12
+  70:	eef12946 	vneg.f16	s5, s12
+  74:	eeb51940 	vcmp.f16	s2, #0.0
+  78:	eeb519c0 	vcmpe.f16	s2, #0.0
+  7c:	eef42966 	vcmp.f16	s5, s13
+  80:	eef429e6 	vcmpe.f16	s5, s13
+  84:	fe4629ab 	vseleq.f16	s5, s13, s23
+  88:	fe6629ab 	vselge.f16	s5, s13, s23
+  8c:	fe5629ab 	vselvs.f16	s5, s13, s23
+  90:	eefd19c4 	vcvt.s32.f16	s3, s8
+  94:	eefc19c4 	vcvt.u32.f16	s3, s8
+  98:	eef819c4 	vcvt.f16.s32	s3, s8
+  9c:	eef81944 	vcvt.f16.u32	s3, s8
+  a0:	eefa39e1 	vcvt.f16.s32	s7, s7, #29
+  a4:	eefb39e1 	vcvt.f16.u32	s7, s7, #29
+  a8:	eefe39e1 	vcvt.s32.f16	s7, s7, #29
+  ac:	eeff39e1 	vcvt.u32.f16	s7, s7, #29
+  b0:	fefc29c5 	vcvta.s32.f16	s5, s10
+  b4:	fefc2945 	vcvta.u32.f16	s5, s10
+  b8:	feff29c5 	vcvtm.s32.f16	s5, s10
+  bc:	feff2945 	vcvtm.u32.f16	s5, s10
+  c0:	fefd29c5 	vcvtn.s32.f16	s5, s10
+  c4:	fefd2945 	vcvtn.u32.f16	s5, s10
+  c8:	fefe29c5 	vcvtp.s32.f16	s5, s10
+  cc:	fefe2945 	vcvtp.u32.f16	s5, s10
+  d0:	eefc2945 	vcvtr.u32.f16	s5, s10
+  d4:	eefd2945 	vcvtr.s32.f16	s5, s10
+  d8:	fef81965 	vrinta.f16	s3, s11
+  dc:	fefb1965 	vrintm.f16	s3, s11
+  e0:	fef91965 	vrintn.f16	s3, s11
+  e4:	fefa1965 	vrintp.f16	s3, s11
+  e8:	eef61965 	vrintr.f16	s3, s11
+  ec:	eef71965 	vrintx.f16	s3, s11
+  f0:	eef619e5 	vrintz.f16	s3, s11
+  f4:	fef02ae4 	vins.f16	s5, s9
+  f8:	fef02a64 	vmovx.f16	s5, s9
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..9b1ab0aaeaabb12764c0498ee41ab09e966116d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
@@ -0,0 +1,75 @@
+#name: ARM v8.2 FP16 support on scalar (Thumb)
+#source: armv8-2-fp16-scalar.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16 -mthumb
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+Disassembly of section .text:
+
+00000000 <label-0xc>:
+   0:	ee00 1910 	vmov.f16	s0, r1
+   4:	ee10 0990 	vmov.f16	r0, s1
+   8:	eeb0 0900 	vmov.f16	s0, #0	; 0x40000000  2.0
+
+0000000c <label>:
+   c:	00000ffe 	.word	0x00000ffe
+  10:	ed5f 1904 	vldr.16	s3, \[pc, #-8\]	; c <label>
+  14:	ed1f 3902 	vldr.16	s6, \[pc, #-4\]	; 14 <label\+0x8>
+  18:	eddf 1902 	vldr.16	s3, \[pc, #4\]	; 20 <label\+0x14>
+  1c:	edd0 0902 	vldr.16	s1, \[r0, #4\]
+  20:	ed10 1902 	vldr.16	s2, \[r0, #-4\]
+  24:	ed80 3902 	vstr.16	s6, \[r0, #4\]
+  28:	ed40 5902 	vstr.16	s11, \[r0, #-4\]
+  2c:	eec6 298c 	vdiv.f16	s5, s13, s24
+  30:	eee6 298c 	vfma.f16	s5, s13, s24
+  34:	eee6 29cc 	vfms.f16	s5, s13, s24
+  38:	eed6 29cc 	vfnma.f16	s5, s13, s24
+  3c:	eed6 298c 	vfnms.f16	s5, s13, s24
+  40:	fec6 298c 	vmaxnm.f16	s5, s13, s24
+  44:	fec6 29cc 	vminnm.f16	s5, s13, s24
+  48:	ee46 298c 	vmla.f16	s5, s13, s24
+  4c:	ee46 29cc 	vmls.f16	s5, s13, s24
+  50:	ee66 298c 	vmul.f16	s5, s13, s24
+  54:	ee56 29cc 	vnmla.f16	s5, s13, s24
+  58:	ee56 298c 	vnmls.f16	s5, s13, s24
+  5c:	ee66 29cc 	vnmul.f16	s5, s13, s24
+  60:	ee76 29cc 	vsub.f16	s5, s13, s24
+  64:	eef0 29c6 	vabs.f16	s5, s12
+  68:	ee72 2986 	vadd.f16	s5, s5, s12
+  6c:	eef1 29c6 	vsqrt.f16	s5, s12
+  70:	eef1 2946 	vneg.f16	s5, s12
+  74:	eeb5 1940 	vcmp.f16	s2, #0.0
+  78:	eeb5 19c0 	vcmpe.f16	s2, #0.0
+  7c:	eef4 2966 	vcmp.f16	s5, s13
+  80:	eef4 29e6 	vcmpe.f16	s5, s13
+  84:	fe46 29ab 	vseleq.f16	s5, s13, s23
+  88:	fe66 29ab 	vselge.f16	s5, s13, s23
+  8c:	fe56 29ab 	vselvs.f16	s5, s13, s23
+  90:	eefd 19c4 	vcvt.s32.f16	s3, s8
+  94:	eefc 19c4 	vcvt.u32.f16	s3, s8
+  98:	eef8 19c4 	vcvt.f16.s32	s3, s8
+  9c:	eef8 1944 	vcvt.f16.u32	s3, s8
+  a0:	eefa 39e1 	vcvt.f16.s32	s7, s7, #29
+  a4:	eefb 39e1 	vcvt.f16.u32	s7, s7, #29
+  a8:	eefe 39e1 	vcvt.s32.f16	s7, s7, #29
+  ac:	eeff 39e1 	vcvt.u32.f16	s7, s7, #29
+  b0:	fefc 29c5 	vcvta.s32.f16	s5, s10
+  b4:	fefc 2945 	vcvta.u32.f16	s5, s10
+  b8:	feff 29c5 	vcvtm.s32.f16	s5, s10
+  bc:	feff 2945 	vcvtm.u32.f16	s5, s10
+  c0:	fefd 29c5 	vcvtn.s32.f16	s5, s10
+  c4:	fefd 2945 	vcvtn.u32.f16	s5, s10
+  c8:	fefe 29c5 	vcvtp.s32.f16	s5, s10
+  cc:	fefe 2945 	vcvtp.u32.f16	s5, s10
+  d0:	eefc 2945 	vcvtr.u32.f16	s5, s10
+  d4:	eefd 2945 	vcvtr.s32.f16	s5, s10
+  d8:	fef8 1965 	vrinta.f16	s3, s11
+  dc:	fefb 1965 	vrintm.f16	s3, s11
+  e0:	fef9 1965 	vrintn.f16	s3, s11
+  e4:	fefa 1965 	vrintp.f16	s3, s11
+  e8:	eef6 1965 	vrintr.f16	s3, s11
+  ec:	eef7 1965 	vrintx.f16	s3, s11
+  f0:	eef6 19e5 	vrintz.f16	s3, s11
+  f4:	fef0 2ae4 	vins.f16	s5, s9
+  f8:	fef0 2a64 	vmovx.f16	s5, s9
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..d551234beaa2467ab33cb5e99a811f11e37629a1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d
@@ -0,0 +1,159 @@
+#name: ARM v8.2 FP16 support on SIMD
+#source: armv8-2-fp16-simd.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00000000 <func>:
+   0:	f3342d0e 	vabd.f16	d2, d4, d14
+   4:	f3384d6c 	vabd.f16	q2, q4, q14
+   8:	f2142f0e 	vmax.f16	d2, d4, d14
+   c:	f2184f6c 	vmax.f16	q2, q4, q14
+  10:	f2342f0e 	vmin.f16	d2, d4, d14
+  14:	f2384f6c 	vmin.f16	q2, q4, q14
+  18:	f3300dec 	vabd.f16	q0, q8, q14
+  1c:	f2100fec 	vmax.f16	q0, q8, q14
+  20:	f2300fec 	vmin.f16	q0, q8, q14
+  24:	f3331d0f 	vabd.f16	d1, d3, d15
+  28:	f3310d08 	vabd.f16	d0, d1, d8
+  2c:	f3b50708 	vabs.f16	d0, d8
+  30:	f3b50760 	vabs.f16	q0, q8
+  34:	f3b50788 	vneg.f16	d0, d8
+  38:	f3b507e0 	vneg.f16	q0, q8
+  3c:	f3b5474c 	vabs.f16	q2, q6
+  40:	f3b547cc 	vneg.f16	q2, q6
+  44:	f3b57703 	vabs.f16	d7, d3
+  48:	f3b59781 	vneg.f16	d9, d1
+  4c:	f3142e1e 	vacge.f16	d2, d4, d14
+  50:	f3184e7c 	vacge.f16	q2, q4, q14
+  54:	f3342e1e 	vacgt.f16	d2, d4, d14
+  58:	f3384e7c 	vacgt.f16	q2, q4, q14
+  5c:	f33e2e14 	vacgt.f16	d2, d14, d4
+  60:	f33c4ed8 	vacgt.f16	q2, q14, q4
+  64:	f31e2e14 	vacge.f16	d2, d14, d4
+  68:	f31c4ed8 	vacge.f16	q2, q14, q4
+  6c:	f2142e0e 	vceq.f16	d2, d4, d14
+  70:	f2184e6c 	vceq.f16	q2, q4, q14
+  74:	f3142e0e 	vcge.f16	d2, d4, d14
+  78:	f3184e6c 	vcge.f16	q2, q4, q14
+  7c:	f3342e0e 	vcgt.f16	d2, d4, d14
+  80:	f3384e6c 	vcgt.f16	q2, q4, q14
+  84:	f31e2e04 	vcge.f16	d2, d14, d4
+  88:	f31c4ec8 	vcge.f16	q2, q14, q4
+  8c:	f33e2e04 	vcgt.f16	d2, d14, d4
+  90:	f33c4ec8 	vcgt.f16	q2, q14, q4
+  94:	f3100efc 	vacge.f16	q0, q8, q14
+  98:	f3300efc 	vacgt.f16	q0, q8, q14
+  9c:	f33c0ef0 	vacgt.f16	q0, q14, q8
+  a0:	f31c0ef0 	vacge.f16	q0, q14, q8
+  a4:	f2100eec 	vceq.f16	q0, q8, q14
+  a8:	f3100eec 	vcge.f16	q0, q8, q14
+  ac:	f3300eec 	vcgt.f16	q0, q8, q14
+  b0:	f31c0ee0 	vcge.f16	q0, q14, q8
+  b4:	f33c0ee0 	vcgt.f16	q0, q14, q8
+  b8:	f2142d0e 	vadd.f16	d2, d4, d14
+  bc:	f2184d6c 	vadd.f16	q2, q4, q14
+  c0:	f2342d0e 	vsub.f16	d2, d4, d14
+  c4:	f2384d6c 	vsub.f16	q2, q4, q14
+  c8:	f2100dec 	vadd.f16	q0, q8, q14
+  cc:	f2300dec 	vsub.f16	q0, q8, q14
+  d0:	f3142f1e 	vmaxnm.f16	d2, d4, d14
+  d4:	f3184f7c 	vmaxnm.f16	q2, q4, q14
+  d8:	f3342f1e 	vminnm.f16	d2, d4, d14
+  dc:	f3384f7c 	vminnm.f16	q2, q4, q14
+  e0:	f2142c1e 	vfma.f16	d2, d4, d14
+  e4:	f2184c7c 	vfma.f16	q2, q4, q14
+  e8:	f2342c1e 	vfms.f16	d2, d4, d14
+  ec:	f2384c7c 	vfms.f16	q2, q4, q14
+  f0:	f2142d1e 	vmla.f16	d2, d4, d14
+  f4:	f2184d7c 	vmla.f16	q2, q4, q14
+  f8:	f2342d1e 	vmls.f16	d2, d4, d14
+  fc:	f2384d7c 	vmls.f16	q2, q4, q14
+ 100:	f3b6458e 	vrintz.f16	d4, d14
+ 104:	f3b685ec 	vrintz.f16	q4, q14
+ 108:	f3b6448e 	vrintx.f16	d4, d14
+ 10c:	f3b684ec 	vrintx.f16	q4, q14
+ 110:	f3b6450e 	vrinta.f16	d4, d14
+ 114:	f3b6856c 	vrinta.f16	q4, q14
+ 118:	f3b6440e 	vrintn.f16	d4, d14
+ 11c:	f3b6846c 	vrintn.f16	q4, q14
+ 120:	f3b6478e 	vrintp.f16	d4, d14
+ 124:	f3b687ec 	vrintp.f16	q4, q14
+ 128:	f3b6468e 	vrintm.f16	d4, d14
+ 12c:	f3b686ec 	vrintm.f16	q4, q14
+ 130:	f3184d0e 	vpadd.f16	d4, d8, d14
+ 134:	f3b74508 	vrecpe.f16	d4, d8
+ 138:	f3b78560 	vrecpe.f16	q4, q8
+ 13c:	f3b74588 	vrsqrte.f16	d4, d8
+ 140:	f3b785e0 	vrsqrte.f16	q4, q8
+ 144:	f3b70564 	vrecpe.f16	q0, q10
+ 148:	f3b705e4 	vrsqrte.f16	q0, q10
+ 14c:	f21a8f1c 	vrecps.f16	d8, d10, d12
+ 150:	f2540ff8 	vrecps.f16	q8, q10, q12
+ 154:	f23a8f1c 	vrsqrts.f16	d8, d10, d12
+ 158:	f2740ff8 	vrsqrts.f16	q8, q10, q12
+ 15c:	f2104f58 	vrecps.f16	q2, q0, q4
+ 160:	f2304f58 	vrsqrts.f16	q2, q0, q4
+ 164:	f3184f0e 	vpmax.f16	d4, d8, d14
+ 168:	f338af02 	vpmin.f16	d10, d8, d2
+ 16c:	f3184d1e 	vmul.f16	d4, d8, d14
+ 170:	f3107d11 	vmul.f16	d7, d0, d1
+ 174:	f3104dd0 	vmul.f16	q2, q8, q0
+ 178:	f3b7600c 	vcvta.s16.f16	d6, d12
+ 17c:	f3b7c068 	vcvta.s16.f16	q6, q12
+ 180:	f3b7630c 	vcvtm.s16.f16	d6, d12
+ 184:	f3b7c368 	vcvtm.s16.f16	q6, q12
+ 188:	f3b7610c 	vcvtn.s16.f16	d6, d12
+ 18c:	f3b7c168 	vcvtn.s16.f16	q6, q12
+ 190:	f3b7620c 	vcvtp.s16.f16	d6, d12
+ 194:	f3b7c268 	vcvtp.s16.f16	q6, q12
+ 198:	f3b7608c 	vcvta.u16.f16	d6, d12
+ 19c:	f3b7c0e8 	vcvta.u16.f16	q6, q12
+ 1a0:	f3b7638c 	vcvtm.u16.f16	d6, d12
+ 1a4:	f3b7c3e8 	vcvtm.u16.f16	q6, q12
+ 1a8:	f3b7618c 	vcvtn.u16.f16	d6, d12
+ 1ac:	f3b7c1e8 	vcvtn.u16.f16	q6, q12
+ 1b0:	f3b7628c 	vcvtp.u16.f16	d6, d12
+ 1b4:	f3b7c2e8 	vcvtp.u16.f16	q6, q12
+ 1b8:	f3b7e700 	vcvt.s16.f16	d14, d0
+ 1bc:	f3f7c740 	vcvt.s16.f16	q14, q0
+ 1c0:	f3b7e780 	vcvt.u16.f16	d14, d0
+ 1c4:	f3f7c7c0 	vcvt.u16.f16	q14, q0
+ 1c8:	f3b7e600 	vcvt.f16.s16	d14, d0
+ 1cc:	f3f7c640 	vcvt.f16.s16	q14, q0
+ 1d0:	f3b7e680 	vcvt.f16.u16	d14, d0
+ 1d4:	f3f7c6c0 	vcvt.f16.u16	q14, q0
+ 1d8:	f2bded10 	vcvt.s16.f16	d14, d0, #3
+ 1dc:	f2fdcd50 	vcvt.s16.f16	q14, q0, #3
+ 1e0:	f3bded10 	vcvt.u16.f16	d14, d0, #3
+ 1e4:	f3fdcd50 	vcvt.u16.f16	q14, q0, #3
+ 1e8:	f2bdec10 	vcvt.f16.s16	d14, d0, #3
+ 1ec:	f2fdcc50 	vcvt.f16.s16	q14, q0, #3
+ 1f0:	f3bdec10 	vcvt.f16.u16	d14, d0, #3
+ 1f4:	f3fdcc50 	vcvt.f16.u16	q14, q0, #3
+ 1f8:	f3b5e502 	vceq.f16	d14, d2, #0
+ 1fc:	f3f5c544 	vceq.f16	q14, q2, #0
+ 200:	f3b5e482 	vcge.f16	d14, d2, #0
+ 204:	f3f5c4c4 	vcge.f16	q14, q2, #0
+ 208:	f3b5e402 	vcgt.f16	d14, d2, #0
+ 20c:	f3f5c444 	vcgt.f16	q14, q2, #0
+ 210:	f3b5e582 	vcle.f16	d14, d2, #0
+ 214:	f3f5c5c4 	vcle.f16	q14, q2, #0
+ 218:	f3b5e602 	vclt.f16	d14, d2, #0
+ 21c:	f3f5c644 	vclt.f16	q14, q2, #0
+ 220:	f2907941 	vmul.f16	d7, d0, d1\[0\]
+ 224:	f2984966 	vmul.f16	d4, d8, d6\[2\]
+ 228:	f39049c8 	vmul.f16	q2, q8, d0\[1\]
+ 22c:	f39049ef 	vmul.f16	q2, q8, d7\[3\]
+ 230:	f2942141 	vmla.f16	d2, d4, d1\[0\]
+ 234:	f3984141 	vmla.f16	q2, q4, d1\[0\]
+ 238:	f2942541 	vmls.f16	d2, d4, d1\[0\]
+ 23c:	f3984541 	vmls.f16	q2, q4, d1\[0\]
+ 240:	f298116f 	vmla.f16	d1, d8, d7\[3\]
+ 244:	f39021ef 	vmla.f16	q1, q8, d7\[3\]
+ 248:	f298156f 	vmls.f16	d1, d8, d7\[3\]
+ 24c:	f39025ef 	vmls.f16	q1, q8, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..5385fe3b67ac3f26919357fd403cf432ddad9c28
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d
@@ -0,0 +1,159 @@
+#name: ARM v8.2 FP16 support on SIMD (Thumb)
+#source: armv8-2-fp16-simd.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16 -mthumb
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00000000 <func>:
+   0:	ff34 2d0e 	vabd.f16	d2, d4, d14
+   4:	ff38 4d6c 	vabd.f16	q2, q4, q14
+   8:	ef14 2f0e 	vmax.f16	d2, d4, d14
+   c:	ef18 4f6c 	vmax.f16	q2, q4, q14
+  10:	ef34 2f0e 	vmin.f16	d2, d4, d14
+  14:	ef38 4f6c 	vmin.f16	q2, q4, q14
+  18:	ff30 0dec 	vabd.f16	q0, q8, q14
+  1c:	ef10 0fec 	vmax.f16	q0, q8, q14
+  20:	ef30 0fec 	vmin.f16	q0, q8, q14
+  24:	ff33 1d0f 	vabd.f16	d1, d3, d15
+  28:	ff31 0d08 	vabd.f16	d0, d1, d8
+  2c:	ffb5 0708 	vabs.f16	d0, d8
+  30:	ffb5 0760 	vabs.f16	q0, q8
+  34:	ffb5 0788 	vneg.f16	d0, d8
+  38:	ffb5 07e0 	vneg.f16	q0, q8
+  3c:	ffb5 474c 	vabs.f16	q2, q6
+  40:	ffb5 47cc 	vneg.f16	q2, q6
+  44:	ffb5 7703 	vabs.f16	d7, d3
+  48:	ffb5 9781 	vneg.f16	d9, d1
+  4c:	ff14 2e1e 	vacge.f16	d2, d4, d14
+  50:	ff18 4e7c 	vacge.f16	q2, q4, q14
+  54:	ff34 2e1e 	vacgt.f16	d2, d4, d14
+  58:	ff38 4e7c 	vacgt.f16	q2, q4, q14
+  5c:	ff3e 2e14 	vacgt.f16	d2, d14, d4
+  60:	ff3c 4ed8 	vacgt.f16	q2, q14, q4
+  64:	ff1e 2e14 	vacge.f16	d2, d14, d4
+  68:	ff1c 4ed8 	vacge.f16	q2, q14, q4
+  6c:	ef14 2e0e 	vceq.f16	d2, d4, d14
+  70:	ef18 4e6c 	vceq.f16	q2, q4, q14
+  74:	ff14 2e0e 	vcge.f16	d2, d4, d14
+  78:	ff18 4e6c 	vcge.f16	q2, q4, q14
+  7c:	ff34 2e0e 	vcgt.f16	d2, d4, d14
+  80:	ff38 4e6c 	vcgt.f16	q2, q4, q14
+  84:	ff1e 2e04 	vcge.f16	d2, d14, d4
+  88:	ff1c 4ec8 	vcge.f16	q2, q14, q4
+  8c:	ff3e 2e04 	vcgt.f16	d2, d14, d4
+  90:	ff3c 4ec8 	vcgt.f16	q2, q14, q4
+  94:	ff10 0efc 	vacge.f16	q0, q8, q14
+  98:	ff30 0efc 	vacgt.f16	q0, q8, q14
+  9c:	ff3c 0ef0 	vacgt.f16	q0, q14, q8
+  a0:	ff1c 0ef0 	vacge.f16	q0, q14, q8
+  a4:	ef10 0eec 	vceq.f16	q0, q8, q14
+  a8:	ff10 0eec 	vcge.f16	q0, q8, q14
+  ac:	ff30 0eec 	vcgt.f16	q0, q8, q14
+  b0:	ff1c 0ee0 	vcge.f16	q0, q14, q8
+  b4:	ff3c 0ee0 	vcgt.f16	q0, q14, q8
+  b8:	ef14 2d0e 	vadd.f16	d2, d4, d14
+  bc:	ef18 4d6c 	vadd.f16	q2, q4, q14
+  c0:	ef34 2d0e 	vsub.f16	d2, d4, d14
+  c4:	ef38 4d6c 	vsub.f16	q2, q4, q14
+  c8:	ef10 0dec 	vadd.f16	q0, q8, q14
+  cc:	ef30 0dec 	vsub.f16	q0, q8, q14
+  d0:	ff14 2f1e 	vmaxnm.f16	d2, d4, d14
+  d4:	ff18 4f7c 	vmaxnm.f16	q2, q4, q14
+  d8:	ff34 2f1e 	vminnm.f16	d2, d4, d14
+  dc:	ff38 4f7c 	vminnm.f16	q2, q4, q14
+  e0:	ef14 2c1e 	vfma.f16	d2, d4, d14
+  e4:	ef18 4c7c 	vfma.f16	q2, q4, q14
+  e8:	ef34 2c1e 	vfms.f16	d2, d4, d14
+  ec:	ef38 4c7c 	vfms.f16	q2, q4, q14
+  f0:	ef14 2d1e 	vmla.f16	d2, d4, d14
+  f4:	ef18 4d7c 	vmla.f16	q2, q4, q14
+  f8:	ef34 2d1e 	vmls.f16	d2, d4, d14
+  fc:	ef38 4d7c 	vmls.f16	q2, q4, q14
+ 100:	ffb6 458e 	vrintz.f16	d4, d14
+ 104:	ffb6 85ec 	vrintz.f16	q4, q14
+ 108:	ffb6 448e 	vrintx.f16	d4, d14
+ 10c:	ffb6 84ec 	vrintx.f16	q4, q14
+ 110:	ffb6 450e 	vrinta.f16	d4, d14
+ 114:	ffb6 856c 	vrinta.f16	q4, q14
+ 118:	ffb6 440e 	vrintn.f16	d4, d14
+ 11c:	ffb6 846c 	vrintn.f16	q4, q14
+ 120:	ffb6 478e 	vrintp.f16	d4, d14
+ 124:	ffb6 87ec 	vrintp.f16	q4, q14
+ 128:	ffb6 468e 	vrintm.f16	d4, d14
+ 12c:	ffb6 86ec 	vrintm.f16	q4, q14
+ 130:	ff18 4d0e 	vpadd.f16	d4, d8, d14
+ 134:	ffb7 4508 	vrecpe.f16	d4, d8
+ 138:	ffb7 8560 	vrecpe.f16	q4, q8
+ 13c:	ffb7 4588 	vrsqrte.f16	d4, d8
+ 140:	ffb7 85e0 	vrsqrte.f16	q4, q8
+ 144:	ffb7 0564 	vrecpe.f16	q0, q10
+ 148:	ffb7 05e4 	vrsqrte.f16	q0, q10
+ 14c:	ef1a 8f1c 	vrecps.f16	d8, d10, d12
+ 150:	ef54 0ff8 	vrecps.f16	q8, q10, q12
+ 154:	ef3a 8f1c 	vrsqrts.f16	d8, d10, d12
+ 158:	ef74 0ff8 	vrsqrts.f16	q8, q10, q12
+ 15c:	ef10 4f58 	vrecps.f16	q2, q0, q4
+ 160:	ef30 4f58 	vrsqrts.f16	q2, q0, q4
+ 164:	ff18 4f0e 	vpmax.f16	d4, d8, d14
+ 168:	ff38 af02 	vpmin.f16	d10, d8, d2
+ 16c:	ff18 4d1e 	vmul.f16	d4, d8, d14
+ 170:	ff10 7d11 	vmul.f16	d7, d0, d1
+ 174:	ff10 4dd0 	vmul.f16	q2, q8, q0
+ 178:	ffb7 600c 	vcvta.s16.f16	d6, d12
+ 17c:	ffb7 c068 	vcvta.s16.f16	q6, q12
+ 180:	ffb7 630c 	vcvtm.s16.f16	d6, d12
+ 184:	ffb7 c368 	vcvtm.s16.f16	q6, q12
+ 188:	ffb7 610c 	vcvtn.s16.f16	d6, d12
+ 18c:	ffb7 c168 	vcvtn.s16.f16	q6, q12
+ 190:	ffb7 620c 	vcvtp.s16.f16	d6, d12
+ 194:	ffb7 c268 	vcvtp.s16.f16	q6, q12
+ 198:	ffb7 608c 	vcvta.u16.f16	d6, d12
+ 19c:	ffb7 c0e8 	vcvta.u16.f16	q6, q12
+ 1a0:	ffb7 638c 	vcvtm.u16.f16	d6, d12
+ 1a4:	ffb7 c3e8 	vcvtm.u16.f16	q6, q12
+ 1a8:	ffb7 618c 	vcvtn.u16.f16	d6, d12
+ 1ac:	ffb7 c1e8 	vcvtn.u16.f16	q6, q12
+ 1b0:	ffb7 628c 	vcvtp.u16.f16	d6, d12
+ 1b4:	ffb7 c2e8 	vcvtp.u16.f16	q6, q12
+ 1b8:	ffb7 e700 	vcvt.s16.f16	d14, d0
+ 1bc:	fff7 c740 	vcvt.s16.f16	q14, q0
+ 1c0:	ffb7 e780 	vcvt.u16.f16	d14, d0
+ 1c4:	fff7 c7c0 	vcvt.u16.f16	q14, q0
+ 1c8:	ffb7 e600 	vcvt.f16.s16	d14, d0
+ 1cc:	fff7 c640 	vcvt.f16.s16	q14, q0
+ 1d0:	ffb7 e680 	vcvt.f16.u16	d14, d0
+ 1d4:	fff7 c6c0 	vcvt.f16.u16	q14, q0
+ 1d8:	efbd ed10 	vcvt.s16.f16	d14, d0, #3
+ 1dc:	effd cd50 	vcvt.s16.f16	q14, q0, #3
+ 1e0:	ffbd ed10 	vcvt.u16.f16	d14, d0, #3
+ 1e4:	fffd cd50 	vcvt.u16.f16	q14, q0, #3
+ 1e8:	efbd ec10 	vcvt.f16.s16	d14, d0, #3
+ 1ec:	effd cc50 	vcvt.f16.s16	q14, q0, #3
+ 1f0:	ffbd ec10 	vcvt.f16.u16	d14, d0, #3
+ 1f4:	fffd cc50 	vcvt.f16.u16	q14, q0, #3
+ 1f8:	ffb5 e502 	vceq.f16	d14, d2, #0
+ 1fc:	fff5 c544 	vceq.f16	q14, q2, #0
+ 200:	ffb5 e482 	vcge.f16	d14, d2, #0
+ 204:	fff5 c4c4 	vcge.f16	q14, q2, #0
+ 208:	ffb5 e402 	vcgt.f16	d14, d2, #0
+ 20c:	fff5 c444 	vcgt.f16	q14, q2, #0
+ 210:	ffb5 e582 	vcle.f16	d14, d2, #0
+ 214:	fff5 c5c4 	vcle.f16	q14, q2, #0
+ 218:	ffb5 e602 	vclt.f16	d14, d2, #0
+ 21c:	fff5 c644 	vclt.f16	q14, q2, #0
+ 220:	ef90 7941 	vmul.f16	d7, d0, d1\[0\]
+ 224:	ef98 4966 	vmul.f16	d4, d8, d6\[2\]
+ 228:	ff90 49c8 	vmul.f16	q2, q8, d0\[1\]
+ 22c:	ff90 49ef 	vmul.f16	q2, q8, d7\[3\]
+ 230:	ef94 2141 	vmla.f16	d2, d4, d1\[0\]
+ 234:	ff98 4141 	vmla.f16	q2, q4, d1\[0\]
+ 238:	ef94 2541 	vmls.f16	d2, d4, d1\[0\]
+ 23c:	ff98 4541 	vmls.f16	q2, q4, d1\[0\]
+ 240:	ef98 116f 	vmla.f16	d1, d8, d7\[3\]
+ 244:	ff90 21ef 	vmla.f16	q1, q8, d7\[3\]
+ 248:	ef98 156f 	vmls.f16	d1, d8, d7\[3\]
+ 24c:	ff90 25ef 	vmls.f16	q1, q8, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..abaeb43619b7e4eeb7a1c937dbfc856a85e603d6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d
@@ -0,0 +1,4 @@
+#name: Reject ARM v8.2 FP16 SIMD instruction for early arch
+#source: armv8-2-fp16-simd.s
+#as: -march=armv8.2-a+simd
+#error_output: armv8-2-fp16-simd-warning.l
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..8f92525704d2bc5a3fbea2a03a274e54b25fccb7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d
@@ -0,0 +1,4 @@
+#name: Reject ARM v8.2 FP16 SIMD instruction for early arch (Thumb)
+#source: armv8-2-fp16-simd.s
+#as: -march=armv8.2-a+simd -mthumb
+#error_output: armv8-2-fp16-simd-warning.l
diff --git a/gas/testsuite/gas/arm/armv8_2+rdma-ext.d b/gas/testsuite/gas/arm/armv8_2+rdma-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..159a5302444a7be477a5649bd4d7f61b9f74923b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2+rdma-ext.d
@@ -0,0 +1,79 @@
+#name: Valid ARMv8.2-A with ARMv8.1-A NEON instructions.
+#as: -march=armv8.2-a+simd
+#objdump: -dr
+#skip: *-*-pe *-*-wince
+#source: armv8-a+rdma.s
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+
+00000000 <.*>:
+   0:	f3110b12 	vqrdmlah.s16	d0, d1, d2
+   4:	f3120b54 	vqrdmlah.s16	q0, q1, q2
+   8:	f3210b12 	vqrdmlah.s32	d0, d1, d2
+   c:	f3220b54 	vqrdmlah.s32	q0, q1, q2
+  10:	f3110c12 	vqrdmlsh.s16	d0, d1, d2
+  14:	f3120c54 	vqrdmlsh.s16	q0, q1, q2
+  18:	f3210c12 	vqrdmlsh.s32	d0, d1, d2
+  1c:	f3220c54 	vqrdmlsh.s32	q0, q1, q2
+  20:	f2910e42 	vqrdmlah.s16	d0, d1, d2\[0\]
+  24:	f2910e4a 	vqrdmlah.s16	d0, d1, d2\[1\]
+  28:	f2910e62 	vqrdmlah.s16	d0, d1, d2\[2\]
+  2c:	f2910e6a 	vqrdmlah.s16	d0, d1, d2\[3\]
+  30:	f3920e42 	vqrdmlah.s16	q0, q1, d2\[0\]
+  34:	f3920e4a 	vqrdmlah.s16	q0, q1, d2\[1\]
+  38:	f3920e62 	vqrdmlah.s16	q0, q1, d2\[2\]
+  3c:	f3920e6a 	vqrdmlah.s16	q0, q1, d2\[3\]
+  40:	f2a10e42 	vqrdmlah.s32	d0, d1, d2\[0\]
+  44:	f2a10e62 	vqrdmlah.s32	d0, d1, d2\[1\]
+  48:	f3a20e42 	vqrdmlah.s32	q0, q1, d2\[0\]
+  4c:	f3a20e62 	vqrdmlah.s32	q0, q1, d2\[1\]
+  50:	f2910f42 	vqrdmlsh.s16	d0, d1, d2\[0\]
+  54:	f2910f4a 	vqrdmlsh.s16	d0, d1, d2\[1\]
+  58:	f2910f62 	vqrdmlsh.s16	d0, d1, d2\[2\]
+  5c:	f2910f6a 	vqrdmlsh.s16	d0, d1, d2\[3\]
+  60:	f3920f42 	vqrdmlsh.s16	q0, q1, d2\[0\]
+  64:	f3920f4a 	vqrdmlsh.s16	q0, q1, d2\[1\]
+  68:	f3920f62 	vqrdmlsh.s16	q0, q1, d2\[2\]
+  6c:	f3920f6a 	vqrdmlsh.s16	q0, q1, d2\[3\]
+  70:	f2a10f42 	vqrdmlsh.s32	d0, d1, d2\[0\]
+  74:	f2a10f62 	vqrdmlsh.s32	d0, d1, d2\[1\]
+  78:	f3a20f42 	vqrdmlsh.s32	q0, q1, d2\[0\]
+  7c:	f3a20f62 	vqrdmlsh.s32	q0, q1, d2\[1\]
+
+00000080 <.*>:
+  80:	ff11 0b12 	vqrdmlah.s16	d0, d1, d2
+  84:	ff12 0b54 	vqrdmlah.s16	q0, q1, q2
+  88:	ff21 0b12 	vqrdmlah.s32	d0, d1, d2
+  8c:	ff22 0b54 	vqrdmlah.s32	q0, q1, q2
+  90:	ff11 0c12 	vqrdmlsh.s16	d0, d1, d2
+  94:	ff12 0c54 	vqrdmlsh.s16	q0, q1, q2
+  98:	ff21 0c12 	vqrdmlsh.s32	d0, d1, d2
+  9c:	ff22 0c54 	vqrdmlsh.s32	q0, q1, q2
+  a0:	ef91 0e42 	vqrdmlah.s16	d0, d1, d2\[0\]
+  a4:	ef91 0e4a 	vqrdmlah.s16	d0, d1, d2\[1\]
+  a8:	ef91 0e62 	vqrdmlah.s16	d0, d1, d2\[2\]
+  ac:	ef91 0e6a 	vqrdmlah.s16	d0, d1, d2\[3\]
+  b0:	ff92 0e42 	vqrdmlah.s16	q0, q1, d2\[0\]
+  b4:	ff92 0e4a 	vqrdmlah.s16	q0, q1, d2\[1\]
+  b8:	ff92 0e62 	vqrdmlah.s16	q0, q1, d2\[2\]
+  bc:	ff92 0e6a 	vqrdmlah.s16	q0, q1, d2\[3\]
+  c0:	efa1 0e42 	vqrdmlah.s32	d0, d1, d2\[0\]
+  c4:	efa1 0e62 	vqrdmlah.s32	d0, d1, d2\[1\]
+  c8:	ffa2 0e42 	vqrdmlah.s32	q0, q1, d2\[0\]
+  cc:	ffa2 0e62 	vqrdmlah.s32	q0, q1, d2\[1\]
+  d0:	ef91 0f42 	vqrdmlsh.s16	d0, d1, d2\[0\]
+  d4:	ef91 0f4a 	vqrdmlsh.s16	d0, d1, d2\[1\]
+  d8:	ef91 0f62 	vqrdmlsh.s16	d0, d1, d2\[2\]
+  dc:	ef91 0f6a 	vqrdmlsh.s16	d0, d1, d2\[3\]
+  e0:	ff92 0f42 	vqrdmlsh.s16	q0, q1, d2\[0\]
+  e4:	ff92 0f4a 	vqrdmlsh.s16	q0, q1, d2\[1\]
+  e8:	ff92 0f62 	vqrdmlsh.s16	q0, q1, d2\[2\]
+  ec:	ff92 0f6a 	vqrdmlsh.s16	q0, q1, d2\[3\]
+  f0:	efa1 0f42 	vqrdmlsh.s32	d0, d1, d2\[0\]
+  f4:	efa1 0f62 	vqrdmlsh.s32	d0, d1, d2\[1\]
+  f8:	ffa2 0f42 	vqrdmlsh.s32	q0, q1, d2\[0\]
+  fc:	ffa2 0f62 	vqrdmlsh.s32	q0, q1, d2\[1\]
+
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d b/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..4b7783ad509fd0e3beab0aa774c14f5dfd1fd274
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.2-a+fp16fml -mthumb
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc21 0810 	vfmal.f16	d0, s2, s0
+.*:	fe00 2810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca1 0810 	vfmsl.f16	d0, s2, s0
+.*:	fe10 2818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc21 0814 	vfmal.f16	d0, s2, s8
+.*:	fe00 2814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca1 0814 	vfmsl.f16	d0, s2, s8
+.*:	fe10 281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc21 0837 	vfmal.f16	d0, s2, s15
+.*:	fe00 2837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca1 0837 	vfmsl.f16	d0, s2, s15
+.*:	fe10 283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc27 0890 	vfmal.f16	d0, s15, s0
+.*:	fe00 f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca7 0890 	vfmsl.f16	d0, s15, s0
+.*:	fe10 f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc27 0894 	vfmal.f16	d0, s15, s8
+.*:	fe00 f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca7 0894 	vfmsl.f16	d0, s15, s8
+.*:	fe10 f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc27 08b7 	vfmal.f16	d0, s15, s15
+.*:	fe00 f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca7 08b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10 f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f 0810 	vfmal.f16	d0, s30, s0
+.*:	fe40 e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf 0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50 e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f 0814 	vfmal.f16	d0, s30, s8
+.*:	fe40 e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf 0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50 e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f 0837 	vfmal.f16	d0, s30, s15
+.*:	fe40 e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf 0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50 e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc21 7810 	vfmal.f16	d7, s2, s0
+.*:	fe03 2890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca1 7810 	vfmsl.f16	d7, s2, s0
+.*:	fe13 2898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc21 7814 	vfmal.f16	d7, s2, s8
+.*:	fe03 2894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca1 7814 	vfmsl.f16	d7, s2, s8
+.*:	fe13 289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc21 7837 	vfmal.f16	d7, s2, s15
+.*:	fe03 28b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca1 7837 	vfmsl.f16	d7, s2, s15
+.*:	fe13 28bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc27 7890 	vfmal.f16	d7, s15, s0
+.*:	fe03 f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca7 7890 	vfmsl.f16	d7, s15, s0
+.*:	fe13 f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc27 7894 	vfmal.f16	d7, s15, s8
+.*:	fe03 f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca7 7894 	vfmsl.f16	d7, s15, s8
+.*:	fe13 f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc27 78b7 	vfmal.f16	d7, s15, s15
+.*:	fe03 f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca7 78b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13 f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f 7810 	vfmal.f16	d7, s30, s0
+.*:	fe43 e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf 7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53 e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f 7814 	vfmal.f16	d7, s30, s8
+.*:	fe43 e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf 7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53 e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f 7837 	vfmal.f16	d7, s30, s15
+.*:	fe43 e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf 7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53 e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc61 0810 	vfmal.f16	d16, s2, s0
+.*:	fe08 2810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce1 0810 	vfmsl.f16	d16, s2, s0
+.*:	fe18 2818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc61 0814 	vfmal.f16	d16, s2, s8
+.*:	fe08 2814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce1 0814 	vfmsl.f16	d16, s2, s8
+.*:	fe18 281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc61 0837 	vfmal.f16	d16, s2, s15
+.*:	fe08 2837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce1 0837 	vfmsl.f16	d16, s2, s15
+.*:	fe18 283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc67 0890 	vfmal.f16	d16, s15, s0
+.*:	fe08 f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce7 0890 	vfmsl.f16	d16, s15, s0
+.*:	fe18 f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc67 0894 	vfmal.f16	d16, s15, s8
+.*:	fe08 f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce7 0894 	vfmsl.f16	d16, s15, s8
+.*:	fe18 f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc67 08b7 	vfmal.f16	d16, s15, s15
+.*:	fe08 f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce7 08b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18 f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f 0810 	vfmal.f16	d16, s30, s0
+.*:	fe48 e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef 0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58 e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f 0814 	vfmal.f16	d16, s30, s8
+.*:	fe48 e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef 0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58 e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f 0837 	vfmal.f16	d16, s30, s15
+.*:	fe48 e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef 0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58 e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61 f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f 2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1 f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f 2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61 f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f 2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1 f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f 289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61 f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f 28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1 f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f 28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67 f890 	vfmal.f16	d31, s15, s0
+.*:	fe0f f890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7 f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1f f898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67 f894 	vfmal.f16	d31, s15, s8
+.*:	fe0f f894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7 f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1f f89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67 f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0f f8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7 f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1f f8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6f f810 	vfmal.f16	d31, s30, s0
+.*:	fe4f e890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fcef f810 	vfmsl.f16	d31, s30, s0
+.*:	fe5f e898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6f f814 	vfmal.f16	d31, s30, s8
+.*:	fe4f e894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fcef f814 	vfmsl.f16	d31, s30, s8
+.*:	fe5f e89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6f f837 	vfmal.f16	d31, s30, s15
+.*:	fe4f e8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fcef f837 	vfmsl.f16	d31, s30, s15
+.*:	fe5f e8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc20 4850 	vfmal.f16	q2, d0, d0
+.*:	fe02 0850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca0 4850 	vfmsl.f16	q2, d0, d0
+.*:	fe12 0878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc20 4857 	vfmal.f16	q2, d0, d7
+.*:	fe02 0857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca0 4857 	vfmsl.f16	q2, d0, d7
+.*:	fe12 087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc20 6850 	vfmal.f16	q3, d0, d0
+.*:	fe03 0850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca0 6850 	vfmsl.f16	q3, d0, d0
+.*:	fe13 0878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc20 6857 	vfmal.f16	q3, d0, d7
+.*:	fe03 0857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca0 6857 	vfmsl.f16	q3, d0, d7
+.*:	fe13 087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60 a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d 0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0 a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d 0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60 a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d 0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0 a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d 087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc21 4850 	vfmal.f16	q2, d1, d0
+.*:	fe02 2850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca1 4850 	vfmsl.f16	q2, d1, d0
+.*:	fe12 2878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc21 4857 	vfmal.f16	q2, d1, d7
+.*:	fe02 2857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca1 4857 	vfmsl.f16	q2, d1, d7
+.*:	fe12 287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc21 6850 	vfmal.f16	q3, d1, d0
+.*:	fe03 2850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca1 6850 	vfmsl.f16	q3, d1, d0
+.*:	fe13 2878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc21 6857 	vfmal.f16	q3, d1, d7
+.*:	fe03 2857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca1 6857 	vfmsl.f16	q3, d1, d7
+.*:	fe13 287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61 a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d 2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1 a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d 2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61 a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d 2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1 a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d 287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc26 4850 	vfmal.f16	q2, d6, d0
+.*:	fe02 c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca6 4850 	vfmsl.f16	q2, d6, d0
+.*:	fe12 c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc26 4857 	vfmal.f16	q2, d6, d7
+.*:	fe02 c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca6 4857 	vfmsl.f16	q2, d6, d7
+.*:	fe12 c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc26 6850 	vfmal.f16	q3, d6, d0
+.*:	fe03 c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca6 6850 	vfmsl.f16	q3, d6, d0
+.*:	fe13 c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc26 6857 	vfmal.f16	q3, d6, d7
+.*:	fe03 c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca6 6857 	vfmsl.f16	q3, d6, d7
+.*:	fe13 c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66 a850 	vfmal.f16	q13, d6, d0
+.*:	fe0d c850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6 a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1d c878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66 a857 	vfmal.f16	q13, d6, d7
+.*:	fe0d c857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6 a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1d c87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f 4850 	vfmal.f16	q2, d15, d0
+.*:	fe42 e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf 4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52 e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f 4857 	vfmal.f16	q2, d15, d7
+.*:	fe42 e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf 4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52 e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f 6850 	vfmal.f16	q3, d15, d0
+.*:	fe43 e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf 6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53 e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f 6857 	vfmal.f16	q3, d15, d7
+.*:	fe43 e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf 6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53 e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6f a850 	vfmal.f16	q13, d15, d0
+.*:	fe4d e850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcef a850 	vfmsl.f16	q13, d15, d0
+.*:	fe5d e878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6f a857 	vfmal.f16	q13, d15, d7
+.*:	fe4d e857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcef a857 	vfmsl.f16	q13, d15, d7
+.*:	fe5d e87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d b/gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..836ecfc5280e1ca326fcd4dc7a3edd6ee1df3023
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.2-a+fp16fml
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc210810 	vfmal.f16	d0, s2, s0
+.*:	fe002810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca10810 	vfmsl.f16	d0, s2, s0
+.*:	fe102818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc210814 	vfmal.f16	d0, s2, s8
+.*:	fe002814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca10814 	vfmsl.f16	d0, s2, s8
+.*:	fe10281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc210837 	vfmal.f16	d0, s2, s15
+.*:	fe002837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca10837 	vfmsl.f16	d0, s2, s15
+.*:	fe10283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc270890 	vfmal.f16	d0, s15, s0
+.*:	fe00f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca70890 	vfmsl.f16	d0, s15, s0
+.*:	fe10f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc270894 	vfmal.f16	d0, s15, s8
+.*:	fe00f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca70894 	vfmsl.f16	d0, s15, s8
+.*:	fe10f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc2708b7 	vfmal.f16	d0, s15, s15
+.*:	fe00f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca708b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f0810 	vfmal.f16	d0, s30, s0
+.*:	fe40e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f0814 	vfmal.f16	d0, s30, s8
+.*:	fe40e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50e81c 	vfmsl.f16	d30, s0, s8\[1\]
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+.*:	fcaf0837 	vfmsl.f16	d0, s30, s15
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+.*:	fc217810 	vfmal.f16	d7, s2, s0
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+.*:	fc217814 	vfmal.f16	d7, s2, s8
+.*:	fe032894 	vfmal.f16	d2, s7, s8\[0\]
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+.*:	fe13289c 	vfmsl.f16	d2, s7, s8\[1\]
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+.*:	fe0328b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca17837 	vfmsl.f16	d7, s2, s15
+.*:	fe1328bf 	vfmsl.f16	d2, s7, s15\[1\]
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+.*:	fca77890 	vfmsl.f16	d7, s15, s0
+.*:	fe13f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc277894 	vfmal.f16	d7, s15, s8
+.*:	fe03f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca77894 	vfmsl.f16	d7, s15, s8
+.*:	fe13f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc2778b7 	vfmal.f16	d7, s15, s15
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+.*:	fca778b7 	vfmsl.f16	d7, s15, s15
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+.*:	fc2f7810 	vfmal.f16	d7, s30, s0
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+.*:	fcaf7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f7814 	vfmal.f16	d7, s30, s8
+.*:	fe43e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f7837 	vfmal.f16	d7, s30, s15
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+.*:	fcaf7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc610810 	vfmal.f16	d16, s2, s0
+.*:	fe082810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce10810 	vfmsl.f16	d16, s2, s0
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+.*:	fc610814 	vfmal.f16	d16, s2, s8
+.*:	fe082814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce10814 	vfmsl.f16	d16, s2, s8
+.*:	fe18281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc610837 	vfmal.f16	d16, s2, s15
+.*:	fe082837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce10837 	vfmsl.f16	d16, s2, s15
+.*:	fe18283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc670890 	vfmal.f16	d16, s15, s0
+.*:	fe08f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce70890 	vfmsl.f16	d16, s15, s0
+.*:	fe18f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc670894 	vfmal.f16	d16, s15, s8
+.*:	fe08f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce70894 	vfmsl.f16	d16, s15, s8
+.*:	fe18f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc6708b7 	vfmal.f16	d16, s15, s15
+.*:	fe08f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce708b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f0810 	vfmal.f16	d16, s30, s0
+.*:	fe48e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f0814 	vfmal.f16	d16, s30, s8
+.*:	fe48e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f0837 	vfmal.f16	d16, s30, s15
+.*:	fe48e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67f890 	vfmal.f16	d31, s15, s0
+.*:	fe0ff890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1ff898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67f894 	vfmal.f16	d31, s15, s8
+.*:	fe0ff894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1ff89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0ff8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1ff8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6ff810 	vfmal.f16	d31, s30, s0
+.*:	fe4fe890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fceff810 	vfmsl.f16	d31, s30, s0
+.*:	fe5fe898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6ff814 	vfmal.f16	d31, s30, s8
+.*:	fe4fe894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fceff814 	vfmsl.f16	d31, s30, s8
+.*:	fe5fe89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6ff837 	vfmal.f16	d31, s30, s15
+.*:	fe4fe8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fceff837 	vfmsl.f16	d31, s30, s15
+.*:	fe5fe8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc204850 	vfmal.f16	q2, d0, d0
+.*:	fe020850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca04850 	vfmsl.f16	q2, d0, d0
+.*:	fe120878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc204857 	vfmal.f16	q2, d0, d7
+.*:	fe020857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca04857 	vfmsl.f16	q2, d0, d7
+.*:	fe12087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc206850 	vfmal.f16	q3, d0, d0
+.*:	fe030850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca06850 	vfmsl.f16	q3, d0, d0
+.*:	fe130878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc206857 	vfmal.f16	q3, d0, d7
+.*:	fe030857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca06857 	vfmsl.f16	q3, d0, d7
+.*:	fe13087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc214850 	vfmal.f16	q2, d1, d0
+.*:	fe022850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca14850 	vfmsl.f16	q2, d1, d0
+.*:	fe122878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc214857 	vfmal.f16	q2, d1, d7
+.*:	fe022857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca14857 	vfmsl.f16	q2, d1, d7
+.*:	fe12287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc216850 	vfmal.f16	q3, d1, d0
+.*:	fe032850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca16850 	vfmsl.f16	q3, d1, d0
+.*:	fe132878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc216857 	vfmal.f16	q3, d1, d7
+.*:	fe032857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca16857 	vfmsl.f16	q3, d1, d7
+.*:	fe13287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc264850 	vfmal.f16	q2, d6, d0
+.*:	fe02c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca64850 	vfmsl.f16	q2, d6, d0
+.*:	fe12c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc264857 	vfmal.f16	q2, d6, d7
+.*:	fe02c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca64857 	vfmsl.f16	q2, d6, d7
+.*:	fe12c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc266850 	vfmal.f16	q3, d6, d0
+.*:	fe03c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca66850 	vfmsl.f16	q3, d6, d0
+.*:	fe13c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc266857 	vfmal.f16	q3, d6, d7
+.*:	fe03c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca66857 	vfmsl.f16	q3, d6, d7
+.*:	fe13c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66a850 	vfmal.f16	q13, d6, d0
+.*:	fe0dc850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1dc878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66a857 	vfmal.f16	q13, d6, d7
+.*:	fe0dc857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1dc87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f4850 	vfmal.f16	q2, d15, d0
+.*:	fe42e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f4857 	vfmal.f16	q2, d15, d7
+.*:	fe42e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f6850 	vfmal.f16	q3, d15, d0
+.*:	fe43e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f6857 	vfmal.f16	q3, d15, d7
+.*:	fe43e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6fa850 	vfmal.f16	q13, d15, d0
+.*:	fe4de850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcefa850 	vfmsl.f16	q13, d15, d0
+.*:	fe5de878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6fa857 	vfmal.f16	q13, d15, d7
+.*:	fe4de857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcefa857 	vfmsl.f16	q13, d15, d7
+.*:	fe5de87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d b/gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..3b1e299649641e279dff47c7a8ef1ced32d7d082
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.3-a+simd
+#source: armv8_3-a-fp-bad.s
+#error_output: armv8_3-a-fp-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-ext.d b/gas/testsuite/gas/arm/armv8_3-a-fp-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..81710e3549328264becceb86026fdb0c32c1a3e1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-ext.d
@@ -0,0 +1,16 @@
+#as: -march=armv8.3-a+simd
+#source: armv8_3-a-fp.s
+#objdump: -dr
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+   [0-9a-f]+:	eef90bc7 	vjcvt.s32.f64	s1, d7
+   [0-9a-f]+:	eef90bc7 	vjcvt.s32.f64	s1, d7
+
+[0-9a-f]+ <.*>:
+   [0-9a-f]+:	eef9 0bc7 	vjcvt.s32.f64	s1, d7
+
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d b/gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..80716b58c29df9751dc58f78d1de626a1e2ba638
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.3-a+fp16fml
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc210810 	vfmal.f16	d0, s2, s0
+.*:	fe002810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca10810 	vfmsl.f16	d0, s2, s0
+.*:	fe102818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc210814 	vfmal.f16	d0, s2, s8
+.*:	fe002814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca10814 	vfmsl.f16	d0, s2, s8
+.*:	fe10281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc210837 	vfmal.f16	d0, s2, s15
+.*:	fe002837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca10837 	vfmsl.f16	d0, s2, s15
+.*:	fe10283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc270890 	vfmal.f16	d0, s15, s0
+.*:	fe00f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca70890 	vfmsl.f16	d0, s15, s0
+.*:	fe10f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc270894 	vfmal.f16	d0, s15, s8
+.*:	fe00f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca70894 	vfmsl.f16	d0, s15, s8
+.*:	fe10f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc2708b7 	vfmal.f16	d0, s15, s15
+.*:	fe00f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca708b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f0810 	vfmal.f16	d0, s30, s0
+.*:	fe40e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f0814 	vfmal.f16	d0, s30, s8
+.*:	fe40e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f0837 	vfmal.f16	d0, s30, s15
+.*:	fe40e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc217810 	vfmal.f16	d7, s2, s0
+.*:	fe032890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca17810 	vfmsl.f16	d7, s2, s0
+.*:	fe132898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc217814 	vfmal.f16	d7, s2, s8
+.*:	fe032894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca17814 	vfmsl.f16	d7, s2, s8
+.*:	fe13289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc217837 	vfmal.f16	d7, s2, s15
+.*:	fe0328b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca17837 	vfmsl.f16	d7, s2, s15
+.*:	fe1328bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc277890 	vfmal.f16	d7, s15, s0
+.*:	fe03f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca77890 	vfmsl.f16	d7, s15, s0
+.*:	fe13f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc277894 	vfmal.f16	d7, s15, s8
+.*:	fe03f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca77894 	vfmsl.f16	d7, s15, s8
+.*:	fe13f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc2778b7 	vfmal.f16	d7, s15, s15
+.*:	fe03f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca778b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f7810 	vfmal.f16	d7, s30, s0
+.*:	fe43e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f7814 	vfmal.f16	d7, s30, s8
+.*:	fe43e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f7837 	vfmal.f16	d7, s30, s15
+.*:	fe43e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc610810 	vfmal.f16	d16, s2, s0
+.*:	fe082810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce10810 	vfmsl.f16	d16, s2, s0
+.*:	fe182818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc610814 	vfmal.f16	d16, s2, s8
+.*:	fe082814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce10814 	vfmsl.f16	d16, s2, s8
+.*:	fe18281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc610837 	vfmal.f16	d16, s2, s15
+.*:	fe082837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce10837 	vfmsl.f16	d16, s2, s15
+.*:	fe18283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc670890 	vfmal.f16	d16, s15, s0
+.*:	fe08f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce70890 	vfmsl.f16	d16, s15, s0
+.*:	fe18f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc670894 	vfmal.f16	d16, s15, s8
+.*:	fe08f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce70894 	vfmsl.f16	d16, s15, s8
+.*:	fe18f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc6708b7 	vfmal.f16	d16, s15, s15
+.*:	fe08f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce708b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f0810 	vfmal.f16	d16, s30, s0
+.*:	fe48e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f0814 	vfmal.f16	d16, s30, s8
+.*:	fe48e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f0837 	vfmal.f16	d16, s30, s15
+.*:	fe48e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67f890 	vfmal.f16	d31, s15, s0
+.*:	fe0ff890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1ff898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67f894 	vfmal.f16	d31, s15, s8
+.*:	fe0ff894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1ff89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0ff8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1ff8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6ff810 	vfmal.f16	d31, s30, s0
+.*:	fe4fe890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fceff810 	vfmsl.f16	d31, s30, s0
+.*:	fe5fe898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6ff814 	vfmal.f16	d31, s30, s8
+.*:	fe4fe894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fceff814 	vfmsl.f16	d31, s30, s8
+.*:	fe5fe89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6ff837 	vfmal.f16	d31, s30, s15
+.*:	fe4fe8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fceff837 	vfmsl.f16	d31, s30, s15
+.*:	fe5fe8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc204850 	vfmal.f16	q2, d0, d0
+.*:	fe020850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca04850 	vfmsl.f16	q2, d0, d0
+.*:	fe120878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc204857 	vfmal.f16	q2, d0, d7
+.*:	fe020857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca04857 	vfmsl.f16	q2, d0, d7
+.*:	fe12087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc206850 	vfmal.f16	q3, d0, d0
+.*:	fe030850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca06850 	vfmsl.f16	q3, d0, d0
+.*:	fe130878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc206857 	vfmal.f16	q3, d0, d7
+.*:	fe030857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca06857 	vfmsl.f16	q3, d0, d7
+.*:	fe13087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc214850 	vfmal.f16	q2, d1, d0
+.*:	fe022850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca14850 	vfmsl.f16	q2, d1, d0
+.*:	fe122878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc214857 	vfmal.f16	q2, d1, d7
+.*:	fe022857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca14857 	vfmsl.f16	q2, d1, d7
+.*:	fe12287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc216850 	vfmal.f16	q3, d1, d0
+.*:	fe032850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca16850 	vfmsl.f16	q3, d1, d0
+.*:	fe132878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc216857 	vfmal.f16	q3, d1, d7
+.*:	fe032857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca16857 	vfmsl.f16	q3, d1, d7
+.*:	fe13287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc264850 	vfmal.f16	q2, d6, d0
+.*:	fe02c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca64850 	vfmsl.f16	q2, d6, d0
+.*:	fe12c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc264857 	vfmal.f16	q2, d6, d7
+.*:	fe02c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca64857 	vfmsl.f16	q2, d6, d7
+.*:	fe12c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc266850 	vfmal.f16	q3, d6, d0
+.*:	fe03c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca66850 	vfmsl.f16	q3, d6, d0
+.*:	fe13c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc266857 	vfmal.f16	q3, d6, d7
+.*:	fe03c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca66857 	vfmsl.f16	q3, d6, d7
+.*:	fe13c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66a850 	vfmal.f16	q13, d6, d0
+.*:	fe0dc850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1dc878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66a857 	vfmal.f16	q13, d6, d7
+.*:	fe0dc857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1dc87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f4850 	vfmal.f16	q2, d15, d0
+.*:	fe42e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f4857 	vfmal.f16	q2, d15, d7
+.*:	fe42e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f6850 	vfmal.f16	q3, d15, d0
+.*:	fe43e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f6857 	vfmal.f16	q3, d15, d7
+.*:	fe43e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6fa850 	vfmal.f16	q13, d15, d0
+.*:	fe4de850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcefa850 	vfmsl.f16	q13, d15, d0
+.*:	fe5de878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6fa857 	vfmal.f16	q13, d15, d7
+.*:	fe4de857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcefa857 	vfmsl.f16	q13, d15, d7
+.*:	fe5de87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d b/gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..a21236771593247030a7e66ff186ad352c61f50a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.3-a+fp16
+#source: armv8_3-a-simd-bad.s
+#error_output: armv8_3-a-simd-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d b/gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..5746bbf814290c4eead5f15c7685a727cc1f5eb8
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d
@@ -0,0 +1,249 @@
+#as: -march=armv8.4-a+fp16
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc210810 	vfmal.f16	d0, s2, s0
+.*:	fe002810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca10810 	vfmsl.f16	d0, s2, s0
+.*:	fe102818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc210814 	vfmal.f16	d0, s2, s8
+.*:	fe002814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca10814 	vfmsl.f16	d0, s2, s8
+.*:	fe10281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc210837 	vfmal.f16	d0, s2, s15
+.*:	fe002837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca10837 	vfmsl.f16	d0, s2, s15
+.*:	fe10283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc270890 	vfmal.f16	d0, s15, s0
+.*:	fe00f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca70890 	vfmsl.f16	d0, s15, s0
+.*:	fe10f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc270894 	vfmal.f16	d0, s15, s8
+.*:	fe00f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca70894 	vfmsl.f16	d0, s15, s8
+.*:	fe10f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc2708b7 	vfmal.f16	d0, s15, s15
+.*:	fe00f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca708b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f0810 	vfmal.f16	d0, s30, s0
+.*:	fe40e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f0814 	vfmal.f16	d0, s30, s8
+.*:	fe40e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f0837 	vfmal.f16	d0, s30, s15
+.*:	fe40e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc217810 	vfmal.f16	d7, s2, s0
+.*:	fe032890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca17810 	vfmsl.f16	d7, s2, s0
+.*:	fe132898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc217814 	vfmal.f16	d7, s2, s8
+.*:	fe032894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca17814 	vfmsl.f16	d7, s2, s8
+.*:	fe13289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc217837 	vfmal.f16	d7, s2, s15
+.*:	fe0328b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca17837 	vfmsl.f16	d7, s2, s15
+.*:	fe1328bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc277890 	vfmal.f16	d7, s15, s0
+.*:	fe03f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca77890 	vfmsl.f16	d7, s15, s0
+.*:	fe13f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc277894 	vfmal.f16	d7, s15, s8
+.*:	fe03f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca77894 	vfmsl.f16	d7, s15, s8
+.*:	fe13f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc2778b7 	vfmal.f16	d7, s15, s15
+.*:	fe03f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca778b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f7810 	vfmal.f16	d7, s30, s0
+.*:	fe43e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f7814 	vfmal.f16	d7, s30, s8
+.*:	fe43e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f7837 	vfmal.f16	d7, s30, s15
+.*:	fe43e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc610810 	vfmal.f16	d16, s2, s0
+.*:	fe082810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce10810 	vfmsl.f16	d16, s2, s0
+.*:	fe182818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc610814 	vfmal.f16	d16, s2, s8
+.*:	fe082814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce10814 	vfmsl.f16	d16, s2, s8
+.*:	fe18281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc610837 	vfmal.f16	d16, s2, s15
+.*:	fe082837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce10837 	vfmsl.f16	d16, s2, s15
+.*:	fe18283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc670890 	vfmal.f16	d16, s15, s0
+.*:	fe08f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce70890 	vfmsl.f16	d16, s15, s0
+.*:	fe18f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc670894 	vfmal.f16	d16, s15, s8
+.*:	fe08f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce70894 	vfmsl.f16	d16, s15, s8
+.*:	fe18f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc6708b7 	vfmal.f16	d16, s15, s15
+.*:	fe08f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce708b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f0810 	vfmal.f16	d16, s30, s0
+.*:	fe48e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f0814 	vfmal.f16	d16, s30, s8
+.*:	fe48e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f0837 	vfmal.f16	d16, s30, s15
+.*:	fe48e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67f890 	vfmal.f16	d31, s15, s0
+.*:	fe0ff890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1ff898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67f894 	vfmal.f16	d31, s15, s8
+.*:	fe0ff894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1ff89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0ff8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1ff8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6ff810 	vfmal.f16	d31, s30, s0
+.*:	fe4fe890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fceff810 	vfmsl.f16	d31, s30, s0
+.*:	fe5fe898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6ff814 	vfmal.f16	d31, s30, s8
+.*:	fe4fe894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fceff814 	vfmsl.f16	d31, s30, s8
+.*:	fe5fe89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6ff837 	vfmal.f16	d31, s30, s15
+.*:	fe4fe8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fceff837 	vfmsl.f16	d31, s30, s15
+.*:	fe5fe8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc204850 	vfmal.f16	q2, d0, d0
+.*:	fe020850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca04850 	vfmsl.f16	q2, d0, d0
+.*:	fe120878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc204857 	vfmal.f16	q2, d0, d7
+.*:	fe020857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca04857 	vfmsl.f16	q2, d0, d7
+.*:	fe12087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc206850 	vfmal.f16	q3, d0, d0
+.*:	fe030850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca06850 	vfmsl.f16	q3, d0, d0
+.*:	fe130878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc206857 	vfmal.f16	q3, d0, d7
+.*:	fe030857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca06857 	vfmsl.f16	q3, d0, d7
+.*:	fe13087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc214850 	vfmal.f16	q2, d1, d0
+.*:	fe022850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca14850 	vfmsl.f16	q2, d1, d0
+.*:	fe122878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc214857 	vfmal.f16	q2, d1, d7
+.*:	fe022857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca14857 	vfmsl.f16	q2, d1, d7
+.*:	fe12287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc216850 	vfmal.f16	q3, d1, d0
+.*:	fe032850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca16850 	vfmsl.f16	q3, d1, d0
+.*:	fe132878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc216857 	vfmal.f16	q3, d1, d7
+.*:	fe032857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca16857 	vfmsl.f16	q3, d1, d7
+.*:	fe13287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc264850 	vfmal.f16	q2, d6, d0
+.*:	fe02c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca64850 	vfmsl.f16	q2, d6, d0
+.*:	fe12c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc264857 	vfmal.f16	q2, d6, d7
+.*:	fe02c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca64857 	vfmsl.f16	q2, d6, d7
+.*:	fe12c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc266850 	vfmal.f16	q3, d6, d0
+.*:	fe03c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca66850 	vfmsl.f16	q3, d6, d0
+.*:	fe13c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc266857 	vfmal.f16	q3, d6, d7
+.*:	fe03c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca66857 	vfmsl.f16	q3, d6, d7
+.*:	fe13c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66a850 	vfmal.f16	q13, d6, d0
+.*:	fe0dc850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1dc878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66a857 	vfmal.f16	q13, d6, d7
+.*:	fe0dc857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1dc87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f4850 	vfmal.f16	q2, d15, d0
+.*:	fe42e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f4857 	vfmal.f16	q2, d15, d7
+.*:	fe42e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f6850 	vfmal.f16	q3, d15, d0
+.*:	fe43e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f6857 	vfmal.f16	q3, d15, d7
+.*:	fe43e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6fa850 	vfmal.f16	q13, d15, d0
+.*:	fe4de850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcefa850 	vfmsl.f16	q13, d15, d0
+.*:	fe5de878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6fa857 	vfmal.f16	q13, d15, d7
+.*:	fe4de857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcefa857 	vfmsl.f16	q13, d15, d7
+.*:	fe5de87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8m.main+fp.d b/gas/testsuite/gas/arm/armv8m.main+fp.d
new file mode 100644
index 0000000000000000000000000000000000000000..cc318e23f7434ca8099aaae34d7b7d4dfaf76202
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8m.main+fp.d
@@ -0,0 +1,32 @@
+#name: Valid armv8-m.main+fp
+#as: -march=armv8-m.main+fp
+#source: fpv5-sp-d16.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
diff --git a/gas/testsuite/gas/arm/armv8m.main+fp.dp.d b/gas/testsuite/gas/arm/armv8m.main+fp.dp.d
new file mode 100644
index 0000000000000000000000000000000000000000..aef81190f3867851ff60179a349d439b449513be
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8m.main+fp.dp.d
@@ -0,0 +1,63 @@
+#name: Valid armv8-m.main+fp.dp
+#as: -march=armv8-m.main+fp.dp
+#source: fpv5-d16.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe00 0b00 	vseleq.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe18 8b08 	vselvs.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe2f fb0f 	vselge.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe3a ab0a 	vselgt.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00 	vmaxnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe88 8b08 	vmaxnm.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe8f fb0f 	vmaxnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe8a ab0a 	vmaxnm.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40 	vminnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe88 8b48 	vminnm.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe8f fb4f 	vminnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe8a ab4a 	vminnm.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> febc 0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0bc8 	vcvtn.s32.f64	s1, d8
+0[0-9a-f]+ <[^>]+> febe fb4f 	vcvtp.u32.f64	s30, d15
+0[0-9a-f]+ <[^>]+> feff fb4a 	vcvtm.u32.f64	s31, d10
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb7 1b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> eeb6 ab4a 	vrintr.f64	d10, d10
+0[0-9a-f]+ <[^>]+> feb8 0b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb9 1b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> feba ab4a 	vrintp.f64	d10, d10
+0[0-9a-f]+ <[^>]+> febb ab4a 	vrintm.f64	d10, d10
+0[0-9a-f]+ <[^>]+> eeb3 0bc0 	vcvtt.f16.f64	s0, d0
+0[0-9a-f]+ <[^>]+> eef3 0b48 	vcvtb.f16.f64	s1, d8
+0[0-9a-f]+ <[^>]+> eeb3 fbcf 	vcvtt.f16.f64	s30, d15
+0[0-9a-f]+ <[^>]+> eef3 fb4a 	vcvtb.f16.f64	s31, d10
+0[0-9a-f]+ <[^>]+> eeb2 0bc0 	vcvtt.f64.f16	d0, s0
+0[0-9a-f]+ <[^>]+> eeb2 8b60 	vcvtb.f64.f16	d8, s1
+0[0-9a-f]+ <[^>]+> eeb2 fbcf 	vcvtt.f64.f16	d15, s30
+0[0-9a-f]+ <[^>]+> eeb2 ab6f 	vcvtb.f64.f16	d10, s31
diff --git a/gas/testsuite/gas/arm/attr-ext-fpv5-d16.d b/gas/testsuite/gas/arm/attr-ext-fpv5-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..eb09cd2ea5e36e4b511c9d5193331e237fed2018
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-fpv5-d16.d
@@ -0,0 +1,14 @@
+# name: attributes for fpv5-d16 using architecture extensions
+# source: blank.s
+# as: -march=armv7e-m+fp.dp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7E-M"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
diff --git a/gas/testsuite/gas/arm/attr-ext-fpv5.d b/gas/testsuite/gas/arm/attr-ext-fpv5.d
new file mode 100644
index 0000000000000000000000000000000000000000..e671e32bcd45a392f86e438e07886187e2c321f2
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-fpv5.d
@@ -0,0 +1,15 @@
+# name: attributes for fpv5 using architecture extensions
+# source: blank.s
+# as: -march=armv7e-m+fpv5
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7E-M"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/attr-ext-idiv.d b/gas/testsuite/gas/arm/attr-ext-idiv.d
new file mode 100644
index 0000000000000000000000000000000000000000..2be50d55278d4f1eb3ca2151371a48c836ae7c52
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-idiv.d
@@ -0,0 +1,15 @@
+# name: attributes for idiv using architecture extensions
+# source: blank.s
+# as: -march=armv7-r+idiv
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-R"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/attr-ext-mp.d b/gas/testsuite/gas/arm/attr-ext-mp.d
new file mode 100644
index 0000000000000000000000000000000000000000..cc3972dc46de01338b6550d5a0a66db72b6bf222
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-mp.d
@@ -0,0 +1,15 @@
+# name: attributes for mp using architecture extensions
+# source: blank.s
+# as: -march=armv7-a+mp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
diff --git a/gas/testsuite/gas/arm/attr-ext-neon-fp16.d b/gas/testsuite/gas/arm/attr-ext-neon-fp16.d
new file mode 100644
index 0000000000000000000000000000000000000000..b35305ff2ae60489ebe5a7850bc312604a67d0b4
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-neon-fp16.d
@@ -0,0 +1,20 @@
+# name: attributes for neon-fp16 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+neon-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
+  Tag_FP_HP_extension: Allowed
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-ext-neon-vfpv3.d b/gas/testsuite/gas/arm/attr-ext-neon-vfpv3.d
new file mode 100644
index 0000000000000000000000000000000000000000..3a5017eb578211ff553467522487c096e078a747
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-neon-vfpv3.d
@@ -0,0 +1,16 @@
+# name: attributes for neon-vfpv3 using architecture extensions
+# source: blank.s
+# as: -march=armv7-a+simd
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
diff --git a/gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d b/gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d
new file mode 100644
index 0000000000000000000000000000000000000000..a41b079f5ec316afe022b4e599f2d4b36ae76946
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d
@@ -0,0 +1,19 @@
+# name: attributes for neon-vfpv4 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+simd
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-ext-sec.d b/gas/testsuite/gas/arm/attr-ext-sec.d
new file mode 100644
index 0000000000000000000000000000000000000000..0e48879a9af8321a659692d65fdd8a8aea425397
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-sec.d
@@ -0,0 +1,15 @@
+# name: attributes for sec using architecture extensions
+# source: blank.s
+# as: -march=armv7-a+sec
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d
new file mode 100644
index 0000000000000000000000000000000000000000..f7150b98e9a7b402365f4a6f895165da217e8afb
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d
@@ -0,0 +1,21 @@
+# name: attributes for architecture extension vfpv3-d16-fp16
+# source: blank.s
+# as: -march=armv7ve+vfpv3-d16-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_FP_HP_extension: Allowed
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
+
+
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..90799e6d80ddd277cab1f86ddfbc1e54da5d03d0
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d
@@ -0,0 +1,14 @@
+# name: attributes for architecture extension vfpv3-d16
+# source: blank.s
+# as: -march=armv7+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7"
+  Tag_CPU_arch: v7
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d b/gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d
new file mode 100644
index 0000000000000000000000000000000000000000..13412319ef5ed0fdf9e4a8d590a9226af4b1aab8
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d
@@ -0,0 +1,20 @@
+# name: attributes for architecture extension vfpv3-fp16
+# source: blank.s
+# as: -march=armv7ve+vfpv3-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_FP_HP_extension: Allowed
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
+
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3.d b/gas/testsuite/gas/arm/attr-ext-vfpv3.d
new file mode 100644
index 0000000000000000000000000000000000000000..7c7ed5388d6e7bd234d3e3263e366f6fa6a09658
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3.d
@@ -0,0 +1,15 @@
+# name: attributes for architecture extension vfpv3
+# source: blank.s
+# as: -march=armv7a+vfpv3
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d b/gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d
new file mode 100644
index 0000000000000000000000000000000000000000..bd510562e76fcbe4c5906eb1891d554de3c0c76e
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d
@@ -0,0 +1,17 @@
+# name: attributes for vfpv3xd-fp16 using architecture extensions
+# source: blank.s
+# as: -march=armv7-r+vfpv3xd-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-R"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_ABI_HardFP_use: SP only
+  Tag_FP_HP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3xd.d b/gas/testsuite/gas/arm/attr-ext-vfpv3xd.d
new file mode 100644
index 0000000000000000000000000000000000000000..3ced8198abf6d5329587babb0b1053b17a16a83a
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3xd.d
@@ -0,0 +1,16 @@
+# name: attributes for vfpv3xd using architecture extensions
+# source: blank.s
+# as: -march=armv7-r+fp.sp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-R"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d b/gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..6e1a160384252954bf402397d71c9d98cae49878
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d
@@ -0,0 +1,18 @@
+# name: attributes for vfpv4-d16 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d b/gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..06bb494da299c893084233825c436e22eeb08852
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d
@@ -0,0 +1,15 @@
+# name: attributes for vfpv4-sp-d16 using architecture extensions
+# source: blank.s
+# as: -march=armv7e-m+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7E-M"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv4.d b/gas/testsuite/gas/arm/attr-ext-vfpv4.d
new file mode 100644
index 0000000000000000000000000000000000000000..397fba340594d763ffb06376ffd15f9032c79a29
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv4.d
@@ -0,0 +1,18 @@
+# name: attributes for vfpv4 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+vfpv4
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d b/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d
index ab729454a0531f3eb4e7c9e95de85d2323740aa8..9a6369aef0ae8524f0a2885b8f24aaf0a1b13f95 100644
--- a/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d
+++ b/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d
@@ -1,14 +1,12 @@
 # name: attributes for -mfpu=neon-fp16
 # source: blank.s
-# as: -mfpu=neon-fp16
+# as: -march=armv7-a+neon-fp16
 # readelf: -A
 # This test is only valid on EABI based ports.
 # target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
+#...
   Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
+  Tag_THUMB_ISA_use: Thumb-2
   Tag_FP_arch: VFPv3
   Tag_Advanced_SIMD_arch: NEONv1
   Tag_FP_HP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/dotprod-mandatory-ext.d b/gas/testsuite/gas/arm/dotprod-mandatory-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..34f6a69ab80e82967f18d7377d5a0604c38270ef
--- /dev/null
+++ b/gas/testsuite/gas/arm/dotprod-mandatory-ext.d
@@ -0,0 +1,297 @@
+#as: -march=armv8.4-a+simd
+#source: dotprod.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc220d10 	vudot.u8	d0, d2, d0
+.*:	fe220d10 	vudot.u8	d0, d2, d0\[0\]
+.*:	fc220d18 	vudot.u8	d0, d2, d8
+.*:	fe220d18 	vudot.u8	d0, d2, d8\[0\]
+.*:	fc220d1f 	vudot.u8	d0, d2, d15
+.*:	fe220d1f 	vudot.u8	d0, d2, d15\[0\]
+.*:	fc2f0d10 	vudot.u8	d0, d15, d0
+.*:	fe2f0d10 	vudot.u8	d0, d15, d0\[0\]
+.*:	fc2f0d18 	vudot.u8	d0, d15, d8
+.*:	fe2f0d18 	vudot.u8	d0, d15, d8\[0\]
+.*:	fc2f0d1f 	vudot.u8	d0, d15, d15
+.*:	fe2f0d1f 	vudot.u8	d0, d15, d15\[0\]
+.*:	fc2e0d90 	vudot.u8	d0, d30, d0
+.*:	fe2e0d90 	vudot.u8	d0, d30, d0\[0\]
+.*:	fc2e0d98 	vudot.u8	d0, d30, d8
+.*:	fe2e0d98 	vudot.u8	d0, d30, d8\[0\]
+.*:	fc2e0d9f 	vudot.u8	d0, d30, d15
+.*:	fe2e0d9f 	vudot.u8	d0, d30, d15\[0\]
+.*:	fc227d10 	vudot.u8	d7, d2, d0
+.*:	fe227d10 	vudot.u8	d7, d2, d0\[0\]
+.*:	fc227d18 	vudot.u8	d7, d2, d8
+.*:	fe227d18 	vudot.u8	d7, d2, d8\[0\]
+.*:	fc227d1f 	vudot.u8	d7, d2, d15
+.*:	fe227d1f 	vudot.u8	d7, d2, d15\[0\]
+.*:	fc2f7d10 	vudot.u8	d7, d15, d0
+.*:	fe2f7d10 	vudot.u8	d7, d15, d0\[0\]
+.*:	fc2f7d18 	vudot.u8	d7, d15, d8
+.*:	fe2f7d18 	vudot.u8	d7, d15, d8\[0\]
+.*:	fc2f7d1f 	vudot.u8	d7, d15, d15
+.*:	fe2f7d1f 	vudot.u8	d7, d15, d15\[0\]
+.*:	fc2e7d90 	vudot.u8	d7, d30, d0
+.*:	fe2e7d90 	vudot.u8	d7, d30, d0\[0\]
+.*:	fc2e7d98 	vudot.u8	d7, d30, d8
+.*:	fe2e7d98 	vudot.u8	d7, d30, d8\[0\]
+.*:	fc2e7d9f 	vudot.u8	d7, d30, d15
+.*:	fe2e7d9f 	vudot.u8	d7, d30, d15\[0\]
+.*:	fc620d10 	vudot.u8	d16, d2, d0
+.*:	fe620d10 	vudot.u8	d16, d2, d0\[0\]
+.*:	fc620d18 	vudot.u8	d16, d2, d8
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+.*:	fc62fd10 	vudot.u8	d31, d2, d0
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+.*:	fc6e0d80 	vsdot.s8	d16, d30, d0
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+.*:	fc62fd00 	vsdot.s8	d31, d2, d0
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+.*:	fe6efd8f 	vsdot.s8	d31, d30, d15\[0\]
+.*:	fc240d50 	vudot.u8	q0, q2, q0
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+.*:	fc2c0dd0 	vudot.u8	q0, q14, q0
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+.*:	fc242d50 	vudot.u8	q1, q2, q0
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+.*:	fc262d50 	vudot.u8	q1, q3, q0
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+.*:	fc2c2dd0 	vudot.u8	q1, q14, q0
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+.*:	fc24cd7e 	vudot.u8	q6, q2, q15
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+.*:	fc26cd50 	vudot.u8	q6, q3, q0
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+.*:	fc2ccdd0 	vudot.u8	q6, q14, q0
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+.*:	fc64ad50 	vudot.u8	q13, q2, q0
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+.*:	fc66ad50 	vudot.u8	q13, q3, q0
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+.*:	fc66ad5e 	vudot.u8	q13, q3, q7
+.*:	fe66ad77 	vudot.u8	q13, q3, d7\[1\]
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+.*:	fc6cadd0 	vudot.u8	q13, q14, q0
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+.*:	fc6cadfe 	vudot.u8	q13, q14, q15
+.*:	fe6cadff 	vudot.u8	q13, q14, d15\[1\]
+.*:	fc240d40 	vsdot.s8	q0, q2, q0
+.*:	fe240d60 	vsdot.s8	q0, q2, d0\[1\]
+.*:	fc240d4e 	vsdot.s8	q0, q2, q7
+.*:	fe240d67 	vsdot.s8	q0, q2, d7\[1\]
+.*:	fc240d6e 	vsdot.s8	q0, q2, q15
+.*:	fe240d6f 	vsdot.s8	q0, q2, d15\[1\]
+.*:	fc260d40 	vsdot.s8	q0, q3, q0
+.*:	fe260d60 	vsdot.s8	q0, q3, d0\[1\]
+.*:	fc260d4e 	vsdot.s8	q0, q3, q7
+.*:	fe260d67 	vsdot.s8	q0, q3, d7\[1\]
+.*:	fc260d6e 	vsdot.s8	q0, q3, q15
+.*:	fe260d6f 	vsdot.s8	q0, q3, d15\[1\]
+.*:	fc2c0dc0 	vsdot.s8	q0, q14, q0
+.*:	fe2c0de0 	vsdot.s8	q0, q14, d0\[1\]
+.*:	fc2c0dce 	vsdot.s8	q0, q14, q7
+.*:	fe2c0de7 	vsdot.s8	q0, q14, d7\[1\]
+.*:	fc2c0dee 	vsdot.s8	q0, q14, q15
+.*:	fe2c0def 	vsdot.s8	q0, q14, d15\[1\]
+.*:	fc242d40 	vsdot.s8	q1, q2, q0
+.*:	fe242d60 	vsdot.s8	q1, q2, d0\[1\]
+.*:	fc242d4e 	vsdot.s8	q1, q2, q7
+.*:	fe242d67 	vsdot.s8	q1, q2, d7\[1\]
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+.*:	fe242d6f 	vsdot.s8	q1, q2, d15\[1\]
+.*:	fc262d40 	vsdot.s8	q1, q3, q0
+.*:	fe262d60 	vsdot.s8	q1, q3, d0\[1\]
+.*:	fc262d4e 	vsdot.s8	q1, q3, q7
+.*:	fe262d67 	vsdot.s8	q1, q3, d7\[1\]
+.*:	fc262d6e 	vsdot.s8	q1, q3, q15
+.*:	fe262d6f 	vsdot.s8	q1, q3, d15\[1\]
+.*:	fc2c2dc0 	vsdot.s8	q1, q14, q0
+.*:	fe2c2de0 	vsdot.s8	q1, q14, d0\[1\]
+.*:	fc2c2dce 	vsdot.s8	q1, q14, q7
+.*:	fe2c2de7 	vsdot.s8	q1, q14, d7\[1\]
+.*:	fc2c2dee 	vsdot.s8	q1, q14, q15
+.*:	fe2c2def 	vsdot.s8	q1, q14, d15\[1\]
+.*:	fc24cd40 	vsdot.s8	q6, q2, q0
+.*:	fe24cd60 	vsdot.s8	q6, q2, d0\[1\]
+.*:	fc24cd4e 	vsdot.s8	q6, q2, q7
+.*:	fe24cd67 	vsdot.s8	q6, q2, d7\[1\]
+.*:	fc24cd6e 	vsdot.s8	q6, q2, q15
+.*:	fe24cd6f 	vsdot.s8	q6, q2, d15\[1\]
+.*:	fc26cd40 	vsdot.s8	q6, q3, q0
+.*:	fe26cd60 	vsdot.s8	q6, q3, d0\[1\]
+.*:	fc26cd4e 	vsdot.s8	q6, q3, q7
+.*:	fe26cd67 	vsdot.s8	q6, q3, d7\[1\]
+.*:	fc26cd6e 	vsdot.s8	q6, q3, q15
+.*:	fe26cd6f 	vsdot.s8	q6, q3, d15\[1\]
+.*:	fc2ccdc0 	vsdot.s8	q6, q14, q0
+.*:	fe2ccde0 	vsdot.s8	q6, q14, d0\[1\]
+.*:	fc2ccdce 	vsdot.s8	q6, q14, q7
+.*:	fe2ccde7 	vsdot.s8	q6, q14, d7\[1\]
+.*:	fc2ccdee 	vsdot.s8	q6, q14, q15
+.*:	fe2ccdef 	vsdot.s8	q6, q14, d15\[1\]
+.*:	fc64ad40 	vsdot.s8	q13, q2, q0
+.*:	fe64ad60 	vsdot.s8	q13, q2, d0\[1\]
+.*:	fc64ad4e 	vsdot.s8	q13, q2, q7
+.*:	fe64ad67 	vsdot.s8	q13, q2, d7\[1\]
+.*:	fc64ad6e 	vsdot.s8	q13, q2, q15
+.*:	fe64ad6f 	vsdot.s8	q13, q2, d15\[1\]
+.*:	fc66ad40 	vsdot.s8	q13, q3, q0
+.*:	fe66ad60 	vsdot.s8	q13, q3, d0\[1\]
+.*:	fc66ad4e 	vsdot.s8	q13, q3, q7
+.*:	fe66ad67 	vsdot.s8	q13, q3, d7\[1\]
+.*:	fc66ad6e 	vsdot.s8	q13, q3, q15
+.*:	fe66ad6f 	vsdot.s8	q13, q3, d15\[1\]
+.*:	fc6cadc0 	vsdot.s8	q13, q14, q0
+.*:	fe6cade0 	vsdot.s8	q13, q14, d0\[1\]
+.*:	fc6cadce 	vsdot.s8	q13, q14, q7
+.*:	fe6cade7 	vsdot.s8	q13, q14, d7\[1\]
+.*:	fc6cadee 	vsdot.s8	q13, q14, q15
+.*:	fe6cadef 	vsdot.s8	q13, q14, d15\[1\]
diff --git a/gas/testsuite/gas/arm/fpv5-d16.s b/gas/testsuite/gas/arm/fpv5-d16.s
new file mode 100644
index 0000000000000000000000000000000000000000..9d9d4d68560f8653a272853f4c0a5b3a3ac51aa1
--- /dev/null
+++ b/gas/testsuite/gas/arm/fpv5-d16.s
@@ -0,0 +1,58 @@
+	.syntax unified
+	.text
+
+	.thumb
+	vseleq.f32	s0, s0, s0
+	vselvs.f32	s1, s1, s1
+	vselge.f32	s30, s30, s30
+	vselgt.f32	s31, s31, s31
+	vseleq.f64	d0, d0, d0
+	vselvs.f64	d8, d8, d8
+	vselge.f64	d15, d15, d15
+	vselgt.f64	d10, d10, d10
+	vmaxnm.f32	s0, s0, s0
+	vmaxnm.f32	s1, s1, s1
+	vmaxnm.f32	s30, s30, s30
+	vmaxnm.f32	s31, s31, s31
+	vmaxnm.f64	d0, d0, d0
+	vmaxnm.f64	d8, d8, d8
+	vmaxnm.f64	d15, d15, d15
+	vmaxnm.f64	d10, d10, d10
+	vminnm.f32	s0, s0, s0
+	vminnm.f32	s1, s1, s1
+	vminnm.f32	s30, s30, s30
+	vminnm.f32	s31, s31, s31
+	vminnm.f64	d0, d0, d0
+	vminnm.f64	d8, d8, d8
+	vminnm.f64	d15, d15, d15
+	vminnm.f64	d10, d10, d10
+	vcvta.s32.f32	s0, s0
+	vcvtn.s32.f32	s1, s1
+	vcvtp.u32.f32	s30, s30
+	vcvtm.u32.f32	s31, s31
+	vcvta.s32.f64	s0, d0
+	vcvtn.s32.f64	s1, d8
+	vcvtp.u32.f64	s30, d15
+	vcvtm.u32.f64	s31, d10
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
+	vrintz.f64	d0, d0
+        vrintx.f64	d1, d1
+        vrintr.f64	d10, d10
+	vrinta.f64	d0, d0
+	vrintn.f64	d1, d1
+	vrintp.f64	d10, d10
+	vrintm.f64	d10, d10
+	vcvtt.f16.f64	s0, d0
+	vcvtb.f16.f64	s1, d8
+	vcvtt.f16.f64	s30, d15
+	vcvtb.f16.f64	s31, d10
+	vcvtt.f64.f16	d0, s0
+	vcvtb.f64.f16	d8, s1
+	vcvtt.f64.f16	d15, s30
+	vcvtb.f64.f16	d10, s31
diff --git a/gas/testsuite/gas/arm/fpv5-sp-d16.s b/gas/testsuite/gas/arm/fpv5-sp-d16.s
new file mode 100644
index 0000000000000000000000000000000000000000..1d9e2439f0cc06bceb46b2de1e67eb1f65d95fe3
--- /dev/null
+++ b/gas/testsuite/gas/arm/fpv5-sp-d16.s
@@ -0,0 +1,27 @@
+	.syntax unified
+	.text
+
+	.thumb
+	vseleq.f32	s0, s0, s0
+	vselvs.f32	s1, s1, s1
+	vselge.f32	s30, s30, s30
+	vselgt.f32	s31, s31, s31
+	vmaxnm.f32	s0, s0, s0
+	vmaxnm.f32	s1, s1, s1
+	vmaxnm.f32	s30, s30, s30
+	vmaxnm.f32	s31, s31, s31
+	vminnm.f32	s0, s0, s0
+	vminnm.f32	s1, s1, s1
+	vminnm.f32	s30, s30, s30
+	vminnm.f32	s31, s31, s31
+	vcvta.s32.f32	s0, s0
+	vcvtn.s32.f32	s1, s1
+	vcvtp.u32.f32	s30, s30
+	vcvtm.u32.f32	s31, s31
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 5888330250494670d5b0e79f552589d309d3c1ac..4f5c89f8383b419832fea1aca0335553cbe4221d 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -205,6 +205,7 @@
 					     | FPU_VFP_EXT_ARMV8xD)
 #define FPU_NEON_ARMV8	  (FPU_NEON_EXT_V1   | FPU_NEON_EXT_FMA	   \
 					     | FPU_NEON_EXT_ARMV8)
+#define FPU_NEON_ARMV8_1  (FPU_NEON_ARMV8    | FPU_NEON_EXT_RDMA)
 #define FPU_CRYPTO_ARMV8  (FPU_CRYPTO_EXT_ARMV8)
 #define FPU_VFP_HARD	  (FPU_VFP_EXT_V1xD  | FPU_VFP_EXT_V1	   \
 					     | FPU_VFP_EXT_V2	   \
@@ -264,19 +265,35 @@
 						    | FPU_NEON_EXT_DOTPROD)
 #define ARCH_CRC_ARMV8		ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
 #define FPU_ARCH_NEON_VFP_ARMV8_1					 \
-				ARM_FEATURE_COPROC (FPU_NEON_ARMV8	 \
-						    | FPU_VFP_ARMV8	 \
-						    | FPU_NEON_EXT_RDMA)
+				ARM_FEATURE_COPROC (FPU_NEON_ARMV8_1	 \
+						    | FPU_VFP_ARMV8)
 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1				 \
 				ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8	 \
-						    | FPU_NEON_ARMV8	 \
-						    | FPU_VFP_ARMV8	 \
-						    | FPU_NEON_EXT_RDMA)
+						    | FPU_NEON_ARMV8_1	 \
+						    | FPU_VFP_ARMV8)
+
 #define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8					 \
 				ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD \
-						    | FPU_NEON_ARMV8	 \
+						    | FPU_NEON_ARMV8_1	 \
 						    | FPU_VFP_ARMV8)
 
+#define FPU_ARCH_NEON_VFP_ARMV8_2_FP16					 \
+      ARM_FEATURE (0, ARM_EXT2_FP16_INST,				 \
+		   FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8)
+
+#define FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML				 \
+      ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML,		 \
+		   FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8)
+
+#define FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML				 \
+      ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML,		 \
+		   FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 | FPU_NEON_EXT_DOTPROD)
+
+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4				 \
+			      ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8	 \
+						  | FPU_NEON_ARMV8_1	 \
+						  | FPU_VFP_ARMV8	 \
+						  | FPU_NEON_EXT_DOTPROD)
 
 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
Nick Clifton March 26, 2019, 3:36 p.m. | #2
Hi Andre,

>> gas/ChangeLog:

>> 2019-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

>>

>>          * config/tc-arm.c (arm_ext_table): New struct type.

>>          (arm_arch_option_table): Add new 'arm_ext_table' field.

>>          (ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.

>>          (armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,

>>           armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,

>>           armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,

>>           armv85a_ext_table, armv8m_main_ext_table,

>>           armv8r_ext_table): New architecture extension tables.

>>          (ARM_ARCH_OPT): Add new default field.

>>          (ARM_ARCH_OPT2): New macro.

>>          (arm_archs): Extend some architectures with the new architecture

>>          extension tables mentioned above.

>>          (arm_extensions): Add DEPRECATED comment with instructions to use new

>>          table.

>>          (arm_parse_extension): Change to use new extension tables.

>>          (arm_parse_cpu): Don't change existing behavior.

>>          (arm_parse_arch): Change to use new extension tables.

>>          * doc/c-arm.texi: Document new architecture extensions.

>>          * testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new

>>          extension option rather than -mfpu and change expected behaviour to

>>          sane outputs.

>>          * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.

>>          * testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.

>>          * testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.

>>          * testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.

>>          * testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.

>>          * testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.

>>          * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.

>>          * testsuite/gas/arm/armv8_2+rdma-ext.d: New.

>>          * testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.

>>          * testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.

>>          * testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.

>>          * testsuite/gas/arm/armv8_3-a-fp-ext.d: New.

>>          * testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.

>>          * testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.

>>          * testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.

>>          * testsuite/gas/arm/armv8m.main+fp.d: New.

>>          * testsuite/gas/arm/armv8m.main+fp.dp.d: New.

>>          * testsuite/gas/arm/attr-ext-fpv5-d16.d: New.

>>          * testsuite/gas/arm/attr-ext-fpv5.d: New.

>>          * testsuite/gas/arm/attr-ext-idiv.d: New.

>>          * testsuite/gas/arm/attr-ext-mp.d: New.

>>          * testsuite/gas/arm/attr-ext-neon-fp16.d: New.

>>          * testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.

>>          * testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.

>>          * testsuite/gas/arm/attr-ext-sec.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv3.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv3xd.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.

>>          * testsuite/gas/arm/attr-ext-vfpv4.d: New.

>>          * testsuite/gas/arm/dotprod-mandatory-ext.d: New.

>>          * testsuite/gas/arm/fpv5-d16.s: New.

>>          * testsuite/gas/arm/fpv5-sp-d16.s: New.

>>

>> include/ChangeLog:

>> 2019-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

>>

>>          * opcode/arm.h (FPU_NEON_ARMV8_1): New.

>>          (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.

>>          (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.

>>          (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.

>>          (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.

>>          (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.

>>          (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.

>>          (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.


Approved - please apply.

Cheers
  Nick

Patch

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5bcd88ba8feb06177a5a909d4405b59861677e21..89d44a46cad3133259aadd09a3f1063418b09606 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -26308,17 +26308,217 @@  static const struct arm_cpu_option_table arm_cpus[] =
 };
 #undef ARM_CPU_OPT
 
+struct arm_ext_table
+{
+  const char *		  name;
+  size_t		  name_len;
+  const arm_feature_set	  merge;
+  const arm_feature_set	  clear;
+};
+
 struct arm_arch_option_table
 {
-  const char *           name;
-  size_t                 name_len;
-  const arm_feature_set	 value;
-  const arm_feature_set	 default_fpu;
+  const char *			name;
+  size_t			name_len;
+  const arm_feature_set		value;
+  const arm_feature_set		default_fpu;
+  const struct arm_ext_table *	ext_table;
+};
+
+/* Used to add support for +E and +noE extension.  */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension.  */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension.  */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+			    ~0 & ~FPU_ENDIAN_PURE)
+
+static const struct arm_ext_table armv5te_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7ve_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
+  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
+  ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
+  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
+  ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
+  ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),  /* Alias for +fp.  */
+  ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
+
+  ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
+	   ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
+
+  /* Aliases for +simd.  */
+  ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
+
+  ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+  ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+  ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
+
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7a_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
+  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp.  */
+  ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
+  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
+  ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
+  ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
+  ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
+
+  ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
+	   ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
+
+  /* Aliases for +simd.  */
+  ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+  ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
+
+  ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
+  ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
+
+  ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
+  ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7r_ext_table[] =
+{
+  ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
+  ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp.  */
+  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
+  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp.  */
+  ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
+  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
+  ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
+	   ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv7em_ext_table[] =
+{
+  ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
+  /* Alias for +fp, used to be known as fpv4-sp-d16.  */
+  ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
+  ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
+  ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
+  ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv8a_ext_table[] =
+{
+  ARM_ADD ("crc", ARCH_CRC_ARMV8),
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation with SIMD, so to the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+
+static const struct arm_ext_table armv81a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation with SIMD, so to the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv82a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
+  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
+  ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+  ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
+
+  /* Armv8-a does not allow an FP implementation with SIMD, so to the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv84a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
+  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation with SIMD, so to the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
+  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv85a_ext_table[] =
+{
+  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
+  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+
+  /* Armv8-a does not allow an FP implementation with SIMD, so to the user
+     should use the +simd option to turn on FP.  */
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv8m_main_ext_table[] =
+{
+  ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+		  ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
+  ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
+  ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table armv8r_ext_table[] =
+{
+  ARM_ADD ("crc", ARCH_CRC_ARMV8),
+  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
+  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
 /* This list should, at a minimum, contain all the architecture names
    recognized by GCC.  */
-#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
+#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
+#define ARM_ARCH_OPT2(N, V, DF, ext) \
+  { N, sizeof (N) - 1, V, DF, ext##_ext_table }
 
 static const struct arm_arch_option_table arm_archs[] =
 {
@@ -26336,50 +26536,51 @@  static const struct arm_arch_option_table arm_archs[] =
   ARM_ARCH_OPT ("armv5",	  ARM_ARCH_V5,		FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv5t",	  ARM_ARCH_V5T,		FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv5txm",	  ARM_ARCH_V5TxM,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_VFP, armv5te),
+  ARM_ARCH_OPT2 ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_VFP,	armv5te),
   /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
      kept to preserve existing behaviour.  */
-  ARM_ARCH_OPT ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_VFP,	armv5te),
   /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
      kept to preserve existing behaviour.  */
-  ARM_ARCH_OPT ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
+  ARM_ARCH_OPT2 ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
   ARM_ARCH_OPT ("armv6-m",	  ARM_ARCH_V6M,		FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6s-m",	  ARM_ARCH_V6SM,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_VFP, armv7),
   /* The official spelling of the ARMv7 profile variants is the dashed form.
      Accept the non-dashed form for compatibility with old toolchains.  */
-  ARM_ARCH_OPT ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
+  ARM_ARCH_OPT2 ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_VFP, armv7ve),
+  ARM_ARCH_OPT2 ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
   ARM_ARCH_OPT ("armv7m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
+  ARM_ARCH_OPT2 ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
   ARM_ARCH_OPT ("armv7-m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_VFP, armv7em),
   ARM_ARCH_OPT ("armv8-m.base",	  ARM_ARCH_V8M_BASE,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8-m.main",	  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv8-m.main",  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP,
+		 armv8m_main),
+  ARM_ARCH_OPT2 ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP, armv8a),
+  ARM_ARCH_OPT2 ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP, armv81a),
+  ARM_ARCH_OPT2 ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP, armv82a),
+  ARM_ARCH_OPT2 ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_VFP, armv82a),
+  ARM_ARCH_OPT2 ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_VFP, armv8r),
+  ARM_ARCH_OPT2 ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_VFP, armv84a),
+  ARM_ARCH_OPT2 ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_VFP, armv85a),
   ARM_ARCH_OPT ("xscale",	  ARM_ARCH_XSCALE,	FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt",	  ARM_ARCH_IWMMXT,	FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt2",	  ARM_ARCH_IWMMXT2,	FPU_ARCH_VFP),
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
 };
 #undef ARM_ARCH_OPT
 
@@ -26402,6 +26603,8 @@  struct arm_option_extension_value_table
 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
 
+/* DEPRECATED: Please do not use this table to add any new extensions, instead
+   use the context sensitive approach using arm_ext_table's.  */
 static const struct arm_option_extension_value_table arm_extensions[] =
 {
   ARM_EXT_OPT ("crc",  ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
@@ -26574,7 +26777,8 @@  struct arm_long_option_table
 
 static bfd_boolean
 arm_parse_extension (const char *str, const arm_feature_set *opt_set,
-		     arm_feature_set *ext_set)
+		     arm_feature_set *ext_set,
+		     const struct arm_ext_table *ext_table)
 {
   /* We insist on extensions being specified in alphabetical order, and with
      extensions being added before being removed.  We achieve this by having
@@ -26640,6 +26844,41 @@  arm_parse_extension (const char *str, const arm_feature_set *opt_set,
       gas_assert (adding_value != -1);
       gas_assert (opt != NULL);
 
+      if (ext_table != NULL)
+	{
+	  const struct arm_ext_table * ext_opt = ext_table;
+	  bfd_boolean found = FALSE;
+	  for (; ext_opt->name != NULL; ext_opt++)
+	    if (ext_opt->name_len == len
+		&& strncmp (ext_opt->name, str, len) == 0)
+	      {
+		if (adding_value)
+		  {
+		    if (ARM_FEATURE_ZERO (ext_opt->merge))
+			/* TODO: Option not supported.  When we remove the
+			   legacy table this case should error out.  */
+			continue;
+
+		    ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
+		  }
+		else
+		  {
+		    if (ARM_FEATURE_ZERO (ext_opt->clear))
+			/* TODO: Option not supported.  When we remove the
+			   legacy table this case should error out.  */
+			continue;
+		    ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
+		  }
+		found = TRUE;
+		break;
+	      }
+	  if (found)
+	    {
+	      str = ext;
+	      continue;
+	    }
+	}
+
       /* Scan over the options table trying to find an exact match. */
       for (; opt->name != NULL; opt++)
 	if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
@@ -26748,7 +26987,7 @@  arm_parse_cpu (const char *str)
 	  }
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt);
+	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
 
 	return TRUE;
       }
@@ -26786,7 +27025,8 @@  arm_parse_arch (const char *str)
 	strcpy (selected_cpu_name, opt->name);
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, march_cpu_opt, march_ext_opt);
+	  return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
+				      opt->ext_table);
 
 	return TRUE;
       }
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 4fb6cadf93526be4736e38cfcac27aa457df40c9..184d7160a887d3512de50255c17bcbb1ba661667 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -248,7 +248,9 @@  names are recognized:
 @code{armv8-r},
 @code{armv8.4-a},
 @code{armv8.5-a},
-@code{iwmmxt}
+@code{armv8-m.base},
+@code{armv8-m.main},
+@code{iwmmxt},
 @code{iwmmxt2}
 and
 @code{xscale}.
@@ -256,8 +258,167 @@  If both @code{-mcpu} and
 @code{-march} are specified, the assembler will use
 the setting for @code{-mcpu}.
 
-The architecture option can be extended with the same instruction set
-extension options as the @code{-mcpu} option.
+The architecture option can be extended with a set extension options.  These
+extensions are context sensitive, i.e. the same extension may mean different
+things when used with different architectures.  When used together with a
+@code{-mfpu} option, the union of both feature enablement is taken.
+See their availability and meaning below:
+
+For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
+
+@code{+fp}: Enables VFPv2 instructions.
+@code{+nofp}: Disables all FPU instrunctions.
+
+For @code{armv7}:
+
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv7-a}:
+
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3-d16}: Alias for @code{+fp}.
+@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
+conversion instructions and 16 double-word registers.
+@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
+instructions and 32 double-word registers.
+@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
+@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
+@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
+registers.
+@code{+neon}: Alias for @code{+simd}.
+@code{+neon-vfpv3}: Alias for @code{+simd}.
+@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
+NEONv1 instructions with 32 double-word registers.
+@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
+double-word registers.
+@code{+mp}: Enables Multiprocessing Extensions.
+@code{+sec}: Enables Security Extensions.
+@code{+nofp}: Disables all FPU and NEON instructions.
+@code{+nosimd}: Disables all NEON instructions.
+
+For @code{armv7ve}:
+
+@code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
+@code{+vfpv4-d16}: Alias for @code{+fp}.
+@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
+conversion instructions and 16 double-word registers.
+@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
+instructions and 32 double-word registers.
+@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
+@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
+double-word registers.
+@code{+neon-vfpv4}: Alias for @code{+simd}.
+@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
+registers.
+@code{+neon-vfpv3}: Alias for @code{+neon}.
+@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
+NEONv1 instructions with 32 double-word registers.
+double-word registers.
+@code{+nofp}: Disables all FPU and NEON instructions.
+@code{+nosimd}: Disables all NEON instructions.
+
+For @code{armv7-r}:
+
+@code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
+double-word registers.
+@code{+vfpv3xd}: Alias for @code{+fp.sp}.
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3-d16}: Alias for @code{+fp}.
+@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
+floating-point conversion instructions with 16 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
+conversion instructions with 16 double-word registers.
+@code{+idiv}: Enables integer division instructions in ARM mode.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv7e-m}:
+
+@code{+fp}: Enables single-precision only VFPv4 instructions with 16
+double-word registers.
+@code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
+@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
+double-word registers.
+@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+fpv5-d16"}: Alias for @code{+fp.dp}.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv8-m.main}:
+
+@code{+dsp}: Enables DSP Extension.
+@code{+fp}: Enables single-precision only VFPv5 instructions with 16
+double-word registers.
+@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+nofp}: Disables all FPU instructions.
+@code{+nodsp}: Disables DSP Extension.
+
+For @code{armv8-a}:
+
+@code{+crc}: Enables CRC32 Extension.
+@code{+simd}: Enables VFP and NEON for Armv8-A.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.1-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.2-a} and @code{armv8.3-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A.
+@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
+@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
+for Armv8.2-A, implies @code{+fp16}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.4-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
+Armv8.2-A.
+@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
+Variant Extensions for Armv8.2-A, implies @code{+simd}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocryptp}: Disables Cryptography Extensions.
+
+For @code{armv8.5-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
+Armv8.2-A.
+@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
+Variant Extensions for Armv8.2-A, implies @code{+simd}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocryptp}: Disables Cryptography Extensions.
+
 
 @cindex @code{-mfpu=} command-line option, ARM
 @item -mfpu=@var{floating-point-format}
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..b98e7cf7b24806b77d70cc56d5f4a6bef040394a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d
@@ -0,0 +1,4 @@ 
+#name: Invalid armv8.2-a scalar fp16
+#source: armv8-2-fp16-scalar-bad.s
+#as: -march=armv8.2-a+fp16
+#error_output: armv8-2-fp16-scalar-bad.l
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..0b5e4e4861c6522e4cc24d63051fad3e9c145939
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d
@@ -0,0 +1,75 @@ 
+#name: ARM v8.2 FP16 support on scalar
+#source: armv8-2-fp16-scalar.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+Disassembly of section .text:
+
+00000000 <label-0xc>:
+   0:	ee001910 	vmov.f16	s0, r1
+   4:	ee100990 	vmov.f16	r0, s1
+   8:	eeb00900 	vmov.f16	s0, #0	; 0x40000000  2.0
+
+0000000c <label>:
+   c:	00000ffe 	.word	0x00000ffe
+  10:	ed5f1906 	vldr.16	s3, \[pc, #-12\]	; c <label>
+  14:	ed1f3902 	vldr.16	s6, \[pc, #-4\]	; 18 <label\+0xc>
+  18:	eddf1902 	vldr.16	s3, \[pc, #4\]	; 24 <label\+0x18>
+  1c:	edd00902 	vldr.16	s1, \[r0, #4\]
+  20:	ed101902 	vldr.16	s2, \[r0, #-4\]
+  24:	ed803902 	vstr.16	s6, \[r0, #4\]
+  28:	ed405902 	vstr.16	s11, \[r0, #-4\]
+  2c:	eec6298c 	vdiv.f16	s5, s13, s24
+  30:	eee6298c 	vfma.f16	s5, s13, s24
+  34:	eee629cc 	vfms.f16	s5, s13, s24
+  38:	eed629cc 	vfnma.f16	s5, s13, s24
+  3c:	eed6298c 	vfnms.f16	s5, s13, s24
+  40:	fec6298c 	vmaxnm.f16	s5, s13, s24
+  44:	fec629cc 	vminnm.f16	s5, s13, s24
+  48:	ee46298c 	vmla.f16	s5, s13, s24
+  4c:	ee4629cc 	vmls.f16	s5, s13, s24
+  50:	ee66298c 	vmul.f16	s5, s13, s24
+  54:	ee5629cc 	vnmla.f16	s5, s13, s24
+  58:	ee56298c 	vnmls.f16	s5, s13, s24
+  5c:	ee6629cc 	vnmul.f16	s5, s13, s24
+  60:	ee7629cc 	vsub.f16	s5, s13, s24
+  64:	eef029c6 	vabs.f16	s5, s12
+  68:	ee722986 	vadd.f16	s5, s5, s12
+  6c:	eef129c6 	vsqrt.f16	s5, s12
+  70:	eef12946 	vneg.f16	s5, s12
+  74:	eeb51940 	vcmp.f16	s2, #0.0
+  78:	eeb519c0 	vcmpe.f16	s2, #0.0
+  7c:	eef42966 	vcmp.f16	s5, s13
+  80:	eef429e6 	vcmpe.f16	s5, s13
+  84:	fe4629ab 	vseleq.f16	s5, s13, s23
+  88:	fe6629ab 	vselge.f16	s5, s13, s23
+  8c:	fe5629ab 	vselvs.f16	s5, s13, s23
+  90:	eefd19c4 	vcvt.s32.f16	s3, s8
+  94:	eefc19c4 	vcvt.u32.f16	s3, s8
+  98:	eef819c4 	vcvt.f16.s32	s3, s8
+  9c:	eef81944 	vcvt.f16.u32	s3, s8
+  a0:	eefa39e1 	vcvt.f16.s32	s7, s7, #29
+  a4:	eefb39e1 	vcvt.f16.u32	s7, s7, #29
+  a8:	eefe39e1 	vcvt.s32.f16	s7, s7, #29
+  ac:	eeff39e1 	vcvt.u32.f16	s7, s7, #29
+  b0:	fefc29c5 	vcvta.s32.f16	s5, s10
+  b4:	fefc2945 	vcvta.u32.f16	s5, s10
+  b8:	feff29c5 	vcvtm.s32.f16	s5, s10
+  bc:	feff2945 	vcvtm.u32.f16	s5, s10
+  c0:	fefd29c5 	vcvtn.s32.f16	s5, s10
+  c4:	fefd2945 	vcvtn.u32.f16	s5, s10
+  c8:	fefe29c5 	vcvtp.s32.f16	s5, s10
+  cc:	fefe2945 	vcvtp.u32.f16	s5, s10
+  d0:	eefc2945 	vcvtr.u32.f16	s5, s10
+  d4:	eefd2945 	vcvtr.s32.f16	s5, s10
+  d8:	fef81965 	vrinta.f16	s3, s11
+  dc:	fefb1965 	vrintm.f16	s3, s11
+  e0:	fef91965 	vrintn.f16	s3, s11
+  e4:	fefa1965 	vrintp.f16	s3, s11
+  e8:	eef61965 	vrintr.f16	s3, s11
+  ec:	eef71965 	vrintx.f16	s3, s11
+  f0:	eef619e5 	vrintz.f16	s3, s11
+  f4:	fef02ae4 	vins.f16	s5, s9
+  f8:	fef02a64 	vmovx.f16	s5, s9
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..9b1ab0aaeaabb12764c0498ee41ab09e966116d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d
@@ -0,0 +1,75 @@ 
+#name: ARM v8.2 FP16 support on scalar (Thumb)
+#source: armv8-2-fp16-scalar.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16 -mthumb
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+Disassembly of section .text:
+
+00000000 <label-0xc>:
+   0:	ee00 1910 	vmov.f16	s0, r1
+   4:	ee10 0990 	vmov.f16	r0, s1
+   8:	eeb0 0900 	vmov.f16	s0, #0	; 0x40000000  2.0
+
+0000000c <label>:
+   c:	00000ffe 	.word	0x00000ffe
+  10:	ed5f 1904 	vldr.16	s3, \[pc, #-8\]	; c <label>
+  14:	ed1f 3902 	vldr.16	s6, \[pc, #-4\]	; 14 <label\+0x8>
+  18:	eddf 1902 	vldr.16	s3, \[pc, #4\]	; 20 <label\+0x14>
+  1c:	edd0 0902 	vldr.16	s1, \[r0, #4\]
+  20:	ed10 1902 	vldr.16	s2, \[r0, #-4\]
+  24:	ed80 3902 	vstr.16	s6, \[r0, #4\]
+  28:	ed40 5902 	vstr.16	s11, \[r0, #-4\]
+  2c:	eec6 298c 	vdiv.f16	s5, s13, s24
+  30:	eee6 298c 	vfma.f16	s5, s13, s24
+  34:	eee6 29cc 	vfms.f16	s5, s13, s24
+  38:	eed6 29cc 	vfnma.f16	s5, s13, s24
+  3c:	eed6 298c 	vfnms.f16	s5, s13, s24
+  40:	fec6 298c 	vmaxnm.f16	s5, s13, s24
+  44:	fec6 29cc 	vminnm.f16	s5, s13, s24
+  48:	ee46 298c 	vmla.f16	s5, s13, s24
+  4c:	ee46 29cc 	vmls.f16	s5, s13, s24
+  50:	ee66 298c 	vmul.f16	s5, s13, s24
+  54:	ee56 29cc 	vnmla.f16	s5, s13, s24
+  58:	ee56 298c 	vnmls.f16	s5, s13, s24
+  5c:	ee66 29cc 	vnmul.f16	s5, s13, s24
+  60:	ee76 29cc 	vsub.f16	s5, s13, s24
+  64:	eef0 29c6 	vabs.f16	s5, s12
+  68:	ee72 2986 	vadd.f16	s5, s5, s12
+  6c:	eef1 29c6 	vsqrt.f16	s5, s12
+  70:	eef1 2946 	vneg.f16	s5, s12
+  74:	eeb5 1940 	vcmp.f16	s2, #0.0
+  78:	eeb5 19c0 	vcmpe.f16	s2, #0.0
+  7c:	eef4 2966 	vcmp.f16	s5, s13
+  80:	eef4 29e6 	vcmpe.f16	s5, s13
+  84:	fe46 29ab 	vseleq.f16	s5, s13, s23
+  88:	fe66 29ab 	vselge.f16	s5, s13, s23
+  8c:	fe56 29ab 	vselvs.f16	s5, s13, s23
+  90:	eefd 19c4 	vcvt.s32.f16	s3, s8
+  94:	eefc 19c4 	vcvt.u32.f16	s3, s8
+  98:	eef8 19c4 	vcvt.f16.s32	s3, s8
+  9c:	eef8 1944 	vcvt.f16.u32	s3, s8
+  a0:	eefa 39e1 	vcvt.f16.s32	s7, s7, #29
+  a4:	eefb 39e1 	vcvt.f16.u32	s7, s7, #29
+  a8:	eefe 39e1 	vcvt.s32.f16	s7, s7, #29
+  ac:	eeff 39e1 	vcvt.u32.f16	s7, s7, #29
+  b0:	fefc 29c5 	vcvta.s32.f16	s5, s10
+  b4:	fefc 2945 	vcvta.u32.f16	s5, s10
+  b8:	feff 29c5 	vcvtm.s32.f16	s5, s10
+  bc:	feff 2945 	vcvtm.u32.f16	s5, s10
+  c0:	fefd 29c5 	vcvtn.s32.f16	s5, s10
+  c4:	fefd 2945 	vcvtn.u32.f16	s5, s10
+  c8:	fefe 29c5 	vcvtp.s32.f16	s5, s10
+  cc:	fefe 2945 	vcvtp.u32.f16	s5, s10
+  d0:	eefc 2945 	vcvtr.u32.f16	s5, s10
+  d4:	eefd 2945 	vcvtr.s32.f16	s5, s10
+  d8:	fef8 1965 	vrinta.f16	s3, s11
+  dc:	fefb 1965 	vrintm.f16	s3, s11
+  e0:	fef9 1965 	vrintn.f16	s3, s11
+  e4:	fefa 1965 	vrintp.f16	s3, s11
+  e8:	eef6 1965 	vrintr.f16	s3, s11
+  ec:	eef7 1965 	vrintx.f16	s3, s11
+  f0:	eef6 19e5 	vrintz.f16	s3, s11
+  f4:	fef0 2ae4 	vins.f16	s5, s9
+  f8:	fef0 2a64 	vmovx.f16	s5, s9
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..d551234beaa2467ab33cb5e99a811f11e37629a1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d
@@ -0,0 +1,159 @@ 
+#name: ARM v8.2 FP16 support on SIMD
+#source: armv8-2-fp16-simd.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00000000 <func>:
+   0:	f3342d0e 	vabd.f16	d2, d4, d14
+   4:	f3384d6c 	vabd.f16	q2, q4, q14
+   8:	f2142f0e 	vmax.f16	d2, d4, d14
+   c:	f2184f6c 	vmax.f16	q2, q4, q14
+  10:	f2342f0e 	vmin.f16	d2, d4, d14
+  14:	f2384f6c 	vmin.f16	q2, q4, q14
+  18:	f3300dec 	vabd.f16	q0, q8, q14
+  1c:	f2100fec 	vmax.f16	q0, q8, q14
+  20:	f2300fec 	vmin.f16	q0, q8, q14
+  24:	f3331d0f 	vabd.f16	d1, d3, d15
+  28:	f3310d08 	vabd.f16	d0, d1, d8
+  2c:	f3b50708 	vabs.f16	d0, d8
+  30:	f3b50760 	vabs.f16	q0, q8
+  34:	f3b50788 	vneg.f16	d0, d8
+  38:	f3b507e0 	vneg.f16	q0, q8
+  3c:	f3b5474c 	vabs.f16	q2, q6
+  40:	f3b547cc 	vneg.f16	q2, q6
+  44:	f3b57703 	vabs.f16	d7, d3
+  48:	f3b59781 	vneg.f16	d9, d1
+  4c:	f3142e1e 	vacge.f16	d2, d4, d14
+  50:	f3184e7c 	vacge.f16	q2, q4, q14
+  54:	f3342e1e 	vacgt.f16	d2, d4, d14
+  58:	f3384e7c 	vacgt.f16	q2, q4, q14
+  5c:	f33e2e14 	vacgt.f16	d2, d14, d4
+  60:	f33c4ed8 	vacgt.f16	q2, q14, q4
+  64:	f31e2e14 	vacge.f16	d2, d14, d4
+  68:	f31c4ed8 	vacge.f16	q2, q14, q4
+  6c:	f2142e0e 	vceq.f16	d2, d4, d14
+  70:	f2184e6c 	vceq.f16	q2, q4, q14
+  74:	f3142e0e 	vcge.f16	d2, d4, d14
+  78:	f3184e6c 	vcge.f16	q2, q4, q14
+  7c:	f3342e0e 	vcgt.f16	d2, d4, d14
+  80:	f3384e6c 	vcgt.f16	q2, q4, q14
+  84:	f31e2e04 	vcge.f16	d2, d14, d4
+  88:	f31c4ec8 	vcge.f16	q2, q14, q4
+  8c:	f33e2e04 	vcgt.f16	d2, d14, d4
+  90:	f33c4ec8 	vcgt.f16	q2, q14, q4
+  94:	f3100efc 	vacge.f16	q0, q8, q14
+  98:	f3300efc 	vacgt.f16	q0, q8, q14
+  9c:	f33c0ef0 	vacgt.f16	q0, q14, q8
+  a0:	f31c0ef0 	vacge.f16	q0, q14, q8
+  a4:	f2100eec 	vceq.f16	q0, q8, q14
+  a8:	f3100eec 	vcge.f16	q0, q8, q14
+  ac:	f3300eec 	vcgt.f16	q0, q8, q14
+  b0:	f31c0ee0 	vcge.f16	q0, q14, q8
+  b4:	f33c0ee0 	vcgt.f16	q0, q14, q8
+  b8:	f2142d0e 	vadd.f16	d2, d4, d14
+  bc:	f2184d6c 	vadd.f16	q2, q4, q14
+  c0:	f2342d0e 	vsub.f16	d2, d4, d14
+  c4:	f2384d6c 	vsub.f16	q2, q4, q14
+  c8:	f2100dec 	vadd.f16	q0, q8, q14
+  cc:	f2300dec 	vsub.f16	q0, q8, q14
+  d0:	f3142f1e 	vmaxnm.f16	d2, d4, d14
+  d4:	f3184f7c 	vmaxnm.f16	q2, q4, q14
+  d8:	f3342f1e 	vminnm.f16	d2, d4, d14
+  dc:	f3384f7c 	vminnm.f16	q2, q4, q14
+  e0:	f2142c1e 	vfma.f16	d2, d4, d14
+  e4:	f2184c7c 	vfma.f16	q2, q4, q14
+  e8:	f2342c1e 	vfms.f16	d2, d4, d14
+  ec:	f2384c7c 	vfms.f16	q2, q4, q14
+  f0:	f2142d1e 	vmla.f16	d2, d4, d14
+  f4:	f2184d7c 	vmla.f16	q2, q4, q14
+  f8:	f2342d1e 	vmls.f16	d2, d4, d14
+  fc:	f2384d7c 	vmls.f16	q2, q4, q14
+ 100:	f3b6458e 	vrintz.f16	d4, d14
+ 104:	f3b685ec 	vrintz.f16	q4, q14
+ 108:	f3b6448e 	vrintx.f16	d4, d14
+ 10c:	f3b684ec 	vrintx.f16	q4, q14
+ 110:	f3b6450e 	vrinta.f16	d4, d14
+ 114:	f3b6856c 	vrinta.f16	q4, q14
+ 118:	f3b6440e 	vrintn.f16	d4, d14
+ 11c:	f3b6846c 	vrintn.f16	q4, q14
+ 120:	f3b6478e 	vrintp.f16	d4, d14
+ 124:	f3b687ec 	vrintp.f16	q4, q14
+ 128:	f3b6468e 	vrintm.f16	d4, d14
+ 12c:	f3b686ec 	vrintm.f16	q4, q14
+ 130:	f3184d0e 	vpadd.f16	d4, d8, d14
+ 134:	f3b74508 	vrecpe.f16	d4, d8
+ 138:	f3b78560 	vrecpe.f16	q4, q8
+ 13c:	f3b74588 	vrsqrte.f16	d4, d8
+ 140:	f3b785e0 	vrsqrte.f16	q4, q8
+ 144:	f3b70564 	vrecpe.f16	q0, q10
+ 148:	f3b705e4 	vrsqrte.f16	q0, q10
+ 14c:	f21a8f1c 	vrecps.f16	d8, d10, d12
+ 150:	f2540ff8 	vrecps.f16	q8, q10, q12
+ 154:	f23a8f1c 	vrsqrts.f16	d8, d10, d12
+ 158:	f2740ff8 	vrsqrts.f16	q8, q10, q12
+ 15c:	f2104f58 	vrecps.f16	q2, q0, q4
+ 160:	f2304f58 	vrsqrts.f16	q2, q0, q4
+ 164:	f3184f0e 	vpmax.f16	d4, d8, d14
+ 168:	f338af02 	vpmin.f16	d10, d8, d2
+ 16c:	f3184d1e 	vmul.f16	d4, d8, d14
+ 170:	f3107d11 	vmul.f16	d7, d0, d1
+ 174:	f3104dd0 	vmul.f16	q2, q8, q0
+ 178:	f3b7600c 	vcvta.s16.f16	d6, d12
+ 17c:	f3b7c068 	vcvta.s16.f16	q6, q12
+ 180:	f3b7630c 	vcvtm.s16.f16	d6, d12
+ 184:	f3b7c368 	vcvtm.s16.f16	q6, q12
+ 188:	f3b7610c 	vcvtn.s16.f16	d6, d12
+ 18c:	f3b7c168 	vcvtn.s16.f16	q6, q12
+ 190:	f3b7620c 	vcvtp.s16.f16	d6, d12
+ 194:	f3b7c268 	vcvtp.s16.f16	q6, q12
+ 198:	f3b7608c 	vcvta.u16.f16	d6, d12
+ 19c:	f3b7c0e8 	vcvta.u16.f16	q6, q12
+ 1a0:	f3b7638c 	vcvtm.u16.f16	d6, d12
+ 1a4:	f3b7c3e8 	vcvtm.u16.f16	q6, q12
+ 1a8:	f3b7618c 	vcvtn.u16.f16	d6, d12
+ 1ac:	f3b7c1e8 	vcvtn.u16.f16	q6, q12
+ 1b0:	f3b7628c 	vcvtp.u16.f16	d6, d12
+ 1b4:	f3b7c2e8 	vcvtp.u16.f16	q6, q12
+ 1b8:	f3b7e700 	vcvt.s16.f16	d14, d0
+ 1bc:	f3f7c740 	vcvt.s16.f16	q14, q0
+ 1c0:	f3b7e780 	vcvt.u16.f16	d14, d0
+ 1c4:	f3f7c7c0 	vcvt.u16.f16	q14, q0
+ 1c8:	f3b7e600 	vcvt.f16.s16	d14, d0
+ 1cc:	f3f7c640 	vcvt.f16.s16	q14, q0
+ 1d0:	f3b7e680 	vcvt.f16.u16	d14, d0
+ 1d4:	f3f7c6c0 	vcvt.f16.u16	q14, q0
+ 1d8:	f2bded10 	vcvt.s16.f16	d14, d0, #3
+ 1dc:	f2fdcd50 	vcvt.s16.f16	q14, q0, #3
+ 1e0:	f3bded10 	vcvt.u16.f16	d14, d0, #3
+ 1e4:	f3fdcd50 	vcvt.u16.f16	q14, q0, #3
+ 1e8:	f2bdec10 	vcvt.f16.s16	d14, d0, #3
+ 1ec:	f2fdcc50 	vcvt.f16.s16	q14, q0, #3
+ 1f0:	f3bdec10 	vcvt.f16.u16	d14, d0, #3
+ 1f4:	f3fdcc50 	vcvt.f16.u16	q14, q0, #3
+ 1f8:	f3b5e502 	vceq.f16	d14, d2, #0
+ 1fc:	f3f5c544 	vceq.f16	q14, q2, #0
+ 200:	f3b5e482 	vcge.f16	d14, d2, #0
+ 204:	f3f5c4c4 	vcge.f16	q14, q2, #0
+ 208:	f3b5e402 	vcgt.f16	d14, d2, #0
+ 20c:	f3f5c444 	vcgt.f16	q14, q2, #0
+ 210:	f3b5e582 	vcle.f16	d14, d2, #0
+ 214:	f3f5c5c4 	vcle.f16	q14, q2, #0
+ 218:	f3b5e602 	vclt.f16	d14, d2, #0
+ 21c:	f3f5c644 	vclt.f16	q14, q2, #0
+ 220:	f2907941 	vmul.f16	d7, d0, d1\[0\]
+ 224:	f2984966 	vmul.f16	d4, d8, d6\[2\]
+ 228:	f39049c8 	vmul.f16	q2, q8, d0\[1\]
+ 22c:	f39049ef 	vmul.f16	q2, q8, d7\[3\]
+ 230:	f2942141 	vmla.f16	d2, d4, d1\[0\]
+ 234:	f3984141 	vmla.f16	q2, q4, d1\[0\]
+ 238:	f2942541 	vmls.f16	d2, d4, d1\[0\]
+ 23c:	f3984541 	vmls.f16	q2, q4, d1\[0\]
+ 240:	f298116f 	vmla.f16	d1, d8, d7\[3\]
+ 244:	f39021ef 	vmla.f16	q1, q8, d7\[3\]
+ 248:	f298156f 	vmls.f16	d1, d8, d7\[3\]
+ 24c:	f39025ef 	vmls.f16	q1, q8, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..5385fe3b67ac3f26919357fd403cf432ddad9c28
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d
@@ -0,0 +1,159 @@ 
+#name: ARM v8.2 FP16 support on SIMD (Thumb)
+#source: armv8-2-fp16-simd.s
+#objdump: -d
+#as: -march=armv8.2-a+fp16 -mthumb
+#skip: *-*-pe *-*-wince
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00000000 <func>:
+   0:	ff34 2d0e 	vabd.f16	d2, d4, d14
+   4:	ff38 4d6c 	vabd.f16	q2, q4, q14
+   8:	ef14 2f0e 	vmax.f16	d2, d4, d14
+   c:	ef18 4f6c 	vmax.f16	q2, q4, q14
+  10:	ef34 2f0e 	vmin.f16	d2, d4, d14
+  14:	ef38 4f6c 	vmin.f16	q2, q4, q14
+  18:	ff30 0dec 	vabd.f16	q0, q8, q14
+  1c:	ef10 0fec 	vmax.f16	q0, q8, q14
+  20:	ef30 0fec 	vmin.f16	q0, q8, q14
+  24:	ff33 1d0f 	vabd.f16	d1, d3, d15
+  28:	ff31 0d08 	vabd.f16	d0, d1, d8
+  2c:	ffb5 0708 	vabs.f16	d0, d8
+  30:	ffb5 0760 	vabs.f16	q0, q8
+  34:	ffb5 0788 	vneg.f16	d0, d8
+  38:	ffb5 07e0 	vneg.f16	q0, q8
+  3c:	ffb5 474c 	vabs.f16	q2, q6
+  40:	ffb5 47cc 	vneg.f16	q2, q6
+  44:	ffb5 7703 	vabs.f16	d7, d3
+  48:	ffb5 9781 	vneg.f16	d9, d1
+  4c:	ff14 2e1e 	vacge.f16	d2, d4, d14
+  50:	ff18 4e7c 	vacge.f16	q2, q4, q14
+  54:	ff34 2e1e 	vacgt.f16	d2, d4, d14
+  58:	ff38 4e7c 	vacgt.f16	q2, q4, q14
+  5c:	ff3e 2e14 	vacgt.f16	d2, d14, d4
+  60:	ff3c 4ed8 	vacgt.f16	q2, q14, q4
+  64:	ff1e 2e14 	vacge.f16	d2, d14, d4
+  68:	ff1c 4ed8 	vacge.f16	q2, q14, q4
+  6c:	ef14 2e0e 	vceq.f16	d2, d4, d14
+  70:	ef18 4e6c 	vceq.f16	q2, q4, q14
+  74:	ff14 2e0e 	vcge.f16	d2, d4, d14
+  78:	ff18 4e6c 	vcge.f16	q2, q4, q14
+  7c:	ff34 2e0e 	vcgt.f16	d2, d4, d14
+  80:	ff38 4e6c 	vcgt.f16	q2, q4, q14
+  84:	ff1e 2e04 	vcge.f16	d2, d14, d4
+  88:	ff1c 4ec8 	vcge.f16	q2, q14, q4
+  8c:	ff3e 2e04 	vcgt.f16	d2, d14, d4
+  90:	ff3c 4ec8 	vcgt.f16	q2, q14, q4
+  94:	ff10 0efc 	vacge.f16	q0, q8, q14
+  98:	ff30 0efc 	vacgt.f16	q0, q8, q14
+  9c:	ff3c 0ef0 	vacgt.f16	q0, q14, q8
+  a0:	ff1c 0ef0 	vacge.f16	q0, q14, q8
+  a4:	ef10 0eec 	vceq.f16	q0, q8, q14
+  a8:	ff10 0eec 	vcge.f16	q0, q8, q14
+  ac:	ff30 0eec 	vcgt.f16	q0, q8, q14
+  b0:	ff1c 0ee0 	vcge.f16	q0, q14, q8
+  b4:	ff3c 0ee0 	vcgt.f16	q0, q14, q8
+  b8:	ef14 2d0e 	vadd.f16	d2, d4, d14
+  bc:	ef18 4d6c 	vadd.f16	q2, q4, q14
+  c0:	ef34 2d0e 	vsub.f16	d2, d4, d14
+  c4:	ef38 4d6c 	vsub.f16	q2, q4, q14
+  c8:	ef10 0dec 	vadd.f16	q0, q8, q14
+  cc:	ef30 0dec 	vsub.f16	q0, q8, q14
+  d0:	ff14 2f1e 	vmaxnm.f16	d2, d4, d14
+  d4:	ff18 4f7c 	vmaxnm.f16	q2, q4, q14
+  d8:	ff34 2f1e 	vminnm.f16	d2, d4, d14
+  dc:	ff38 4f7c 	vminnm.f16	q2, q4, q14
+  e0:	ef14 2c1e 	vfma.f16	d2, d4, d14
+  e4:	ef18 4c7c 	vfma.f16	q2, q4, q14
+  e8:	ef34 2c1e 	vfms.f16	d2, d4, d14
+  ec:	ef38 4c7c 	vfms.f16	q2, q4, q14
+  f0:	ef14 2d1e 	vmla.f16	d2, d4, d14
+  f4:	ef18 4d7c 	vmla.f16	q2, q4, q14
+  f8:	ef34 2d1e 	vmls.f16	d2, d4, d14
+  fc:	ef38 4d7c 	vmls.f16	q2, q4, q14
+ 100:	ffb6 458e 	vrintz.f16	d4, d14
+ 104:	ffb6 85ec 	vrintz.f16	q4, q14
+ 108:	ffb6 448e 	vrintx.f16	d4, d14
+ 10c:	ffb6 84ec 	vrintx.f16	q4, q14
+ 110:	ffb6 450e 	vrinta.f16	d4, d14
+ 114:	ffb6 856c 	vrinta.f16	q4, q14
+ 118:	ffb6 440e 	vrintn.f16	d4, d14
+ 11c:	ffb6 846c 	vrintn.f16	q4, q14
+ 120:	ffb6 478e 	vrintp.f16	d4, d14
+ 124:	ffb6 87ec 	vrintp.f16	q4, q14
+ 128:	ffb6 468e 	vrintm.f16	d4, d14
+ 12c:	ffb6 86ec 	vrintm.f16	q4, q14
+ 130:	ff18 4d0e 	vpadd.f16	d4, d8, d14
+ 134:	ffb7 4508 	vrecpe.f16	d4, d8
+ 138:	ffb7 8560 	vrecpe.f16	q4, q8
+ 13c:	ffb7 4588 	vrsqrte.f16	d4, d8
+ 140:	ffb7 85e0 	vrsqrte.f16	q4, q8
+ 144:	ffb7 0564 	vrecpe.f16	q0, q10
+ 148:	ffb7 05e4 	vrsqrte.f16	q0, q10
+ 14c:	ef1a 8f1c 	vrecps.f16	d8, d10, d12
+ 150:	ef54 0ff8 	vrecps.f16	q8, q10, q12
+ 154:	ef3a 8f1c 	vrsqrts.f16	d8, d10, d12
+ 158:	ef74 0ff8 	vrsqrts.f16	q8, q10, q12
+ 15c:	ef10 4f58 	vrecps.f16	q2, q0, q4
+ 160:	ef30 4f58 	vrsqrts.f16	q2, q0, q4
+ 164:	ff18 4f0e 	vpmax.f16	d4, d8, d14
+ 168:	ff38 af02 	vpmin.f16	d10, d8, d2
+ 16c:	ff18 4d1e 	vmul.f16	d4, d8, d14
+ 170:	ff10 7d11 	vmul.f16	d7, d0, d1
+ 174:	ff10 4dd0 	vmul.f16	q2, q8, q0
+ 178:	ffb7 600c 	vcvta.s16.f16	d6, d12
+ 17c:	ffb7 c068 	vcvta.s16.f16	q6, q12
+ 180:	ffb7 630c 	vcvtm.s16.f16	d6, d12
+ 184:	ffb7 c368 	vcvtm.s16.f16	q6, q12
+ 188:	ffb7 610c 	vcvtn.s16.f16	d6, d12
+ 18c:	ffb7 c168 	vcvtn.s16.f16	q6, q12
+ 190:	ffb7 620c 	vcvtp.s16.f16	d6, d12
+ 194:	ffb7 c268 	vcvtp.s16.f16	q6, q12
+ 198:	ffb7 608c 	vcvta.u16.f16	d6, d12
+ 19c:	ffb7 c0e8 	vcvta.u16.f16	q6, q12
+ 1a0:	ffb7 638c 	vcvtm.u16.f16	d6, d12
+ 1a4:	ffb7 c3e8 	vcvtm.u16.f16	q6, q12
+ 1a8:	ffb7 618c 	vcvtn.u16.f16	d6, d12
+ 1ac:	ffb7 c1e8 	vcvtn.u16.f16	q6, q12
+ 1b0:	ffb7 628c 	vcvtp.u16.f16	d6, d12
+ 1b4:	ffb7 c2e8 	vcvtp.u16.f16	q6, q12
+ 1b8:	ffb7 e700 	vcvt.s16.f16	d14, d0
+ 1bc:	fff7 c740 	vcvt.s16.f16	q14, q0
+ 1c0:	ffb7 e780 	vcvt.u16.f16	d14, d0
+ 1c4:	fff7 c7c0 	vcvt.u16.f16	q14, q0
+ 1c8:	ffb7 e600 	vcvt.f16.s16	d14, d0
+ 1cc:	fff7 c640 	vcvt.f16.s16	q14, q0
+ 1d0:	ffb7 e680 	vcvt.f16.u16	d14, d0
+ 1d4:	fff7 c6c0 	vcvt.f16.u16	q14, q0
+ 1d8:	efbd ed10 	vcvt.s16.f16	d14, d0, #3
+ 1dc:	effd cd50 	vcvt.s16.f16	q14, q0, #3
+ 1e0:	ffbd ed10 	vcvt.u16.f16	d14, d0, #3
+ 1e4:	fffd cd50 	vcvt.u16.f16	q14, q0, #3
+ 1e8:	efbd ec10 	vcvt.f16.s16	d14, d0, #3
+ 1ec:	effd cc50 	vcvt.f16.s16	q14, q0, #3
+ 1f0:	ffbd ec10 	vcvt.f16.u16	d14, d0, #3
+ 1f4:	fffd cc50 	vcvt.f16.u16	q14, q0, #3
+ 1f8:	ffb5 e502 	vceq.f16	d14, d2, #0
+ 1fc:	fff5 c544 	vceq.f16	q14, q2, #0
+ 200:	ffb5 e482 	vcge.f16	d14, d2, #0
+ 204:	fff5 c4c4 	vcge.f16	q14, q2, #0
+ 208:	ffb5 e402 	vcgt.f16	d14, d2, #0
+ 20c:	fff5 c444 	vcgt.f16	q14, q2, #0
+ 210:	ffb5 e582 	vcle.f16	d14, d2, #0
+ 214:	fff5 c5c4 	vcle.f16	q14, q2, #0
+ 218:	ffb5 e602 	vclt.f16	d14, d2, #0
+ 21c:	fff5 c644 	vclt.f16	q14, q2, #0
+ 220:	ef90 7941 	vmul.f16	d7, d0, d1\[0\]
+ 224:	ef98 4966 	vmul.f16	d4, d8, d6\[2\]
+ 228:	ff90 49c8 	vmul.f16	q2, q8, d0\[1\]
+ 22c:	ff90 49ef 	vmul.f16	q2, q8, d7\[3\]
+ 230:	ef94 2141 	vmla.f16	d2, d4, d1\[0\]
+ 234:	ff98 4141 	vmla.f16	q2, q4, d1\[0\]
+ 238:	ef94 2541 	vmls.f16	d2, d4, d1\[0\]
+ 23c:	ff98 4541 	vmls.f16	q2, q4, d1\[0\]
+ 240:	ef98 116f 	vmla.f16	d1, d8, d7\[3\]
+ 244:	ff90 21ef 	vmla.f16	q1, q8, d7\[3\]
+ 248:	ef98 156f 	vmls.f16	d1, d8, d7\[3\]
+ 24c:	ff90 25ef 	vmls.f16	q1, q8, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..abaeb43619b7e4eeb7a1c937dbfc856a85e603d6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d
@@ -0,0 +1,4 @@ 
+#name: Reject ARM v8.2 FP16 SIMD instruction for early arch
+#source: armv8-2-fp16-simd.s
+#as: -march=armv8.2-a+simd
+#error_output: armv8-2-fp16-simd-warning.l
diff --git a/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..8f92525704d2bc5a3fbea2a03a274e54b25fccb7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d
@@ -0,0 +1,4 @@ 
+#name: Reject ARM v8.2 FP16 SIMD instruction for early arch (Thumb)
+#source: armv8-2-fp16-simd.s
+#as: -march=armv8.2-a+simd -mthumb
+#error_output: armv8-2-fp16-simd-warning.l
diff --git a/gas/testsuite/gas/arm/armv8_2+rdma-ext.d b/gas/testsuite/gas/arm/armv8_2+rdma-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..159a5302444a7be477a5649bd4d7f61b9f74923b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2+rdma-ext.d
@@ -0,0 +1,79 @@ 
+#name: Valid ARMv8.2-A with ARMv8.1-A NEON instructions.
+#as: -march=armv8.2-a+simd
+#objdump: -dr
+#skip: *-*-pe *-*-wince
+#source: armv8-a+rdma.s
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+
+00000000 <.*>:
+   0:	f3110b12 	vqrdmlah.s16	d0, d1, d2
+   4:	f3120b54 	vqrdmlah.s16	q0, q1, q2
+   8:	f3210b12 	vqrdmlah.s32	d0, d1, d2
+   c:	f3220b54 	vqrdmlah.s32	q0, q1, q2
+  10:	f3110c12 	vqrdmlsh.s16	d0, d1, d2
+  14:	f3120c54 	vqrdmlsh.s16	q0, q1, q2
+  18:	f3210c12 	vqrdmlsh.s32	d0, d1, d2
+  1c:	f3220c54 	vqrdmlsh.s32	q0, q1, q2
+  20:	f2910e42 	vqrdmlah.s16	d0, d1, d2\[0\]
+  24:	f2910e4a 	vqrdmlah.s16	d0, d1, d2\[1\]
+  28:	f2910e62 	vqrdmlah.s16	d0, d1, d2\[2\]
+  2c:	f2910e6a 	vqrdmlah.s16	d0, d1, d2\[3\]
+  30:	f3920e42 	vqrdmlah.s16	q0, q1, d2\[0\]
+  34:	f3920e4a 	vqrdmlah.s16	q0, q1, d2\[1\]
+  38:	f3920e62 	vqrdmlah.s16	q0, q1, d2\[2\]
+  3c:	f3920e6a 	vqrdmlah.s16	q0, q1, d2\[3\]
+  40:	f2a10e42 	vqrdmlah.s32	d0, d1, d2\[0\]
+  44:	f2a10e62 	vqrdmlah.s32	d0, d1, d2\[1\]
+  48:	f3a20e42 	vqrdmlah.s32	q0, q1, d2\[0\]
+  4c:	f3a20e62 	vqrdmlah.s32	q0, q1, d2\[1\]
+  50:	f2910f42 	vqrdmlsh.s16	d0, d1, d2\[0\]
+  54:	f2910f4a 	vqrdmlsh.s16	d0, d1, d2\[1\]
+  58:	f2910f62 	vqrdmlsh.s16	d0, d1, d2\[2\]
+  5c:	f2910f6a 	vqrdmlsh.s16	d0, d1, d2\[3\]
+  60:	f3920f42 	vqrdmlsh.s16	q0, q1, d2\[0\]
+  64:	f3920f4a 	vqrdmlsh.s16	q0, q1, d2\[1\]
+  68:	f3920f62 	vqrdmlsh.s16	q0, q1, d2\[2\]
+  6c:	f3920f6a 	vqrdmlsh.s16	q0, q1, d2\[3\]
+  70:	f2a10f42 	vqrdmlsh.s32	d0, d1, d2\[0\]
+  74:	f2a10f62 	vqrdmlsh.s32	d0, d1, d2\[1\]
+  78:	f3a20f42 	vqrdmlsh.s32	q0, q1, d2\[0\]
+  7c:	f3a20f62 	vqrdmlsh.s32	q0, q1, d2\[1\]
+
+00000080 <.*>:
+  80:	ff11 0b12 	vqrdmlah.s16	d0, d1, d2
+  84:	ff12 0b54 	vqrdmlah.s16	q0, q1, q2
+  88:	ff21 0b12 	vqrdmlah.s32	d0, d1, d2
+  8c:	ff22 0b54 	vqrdmlah.s32	q0, q1, q2
+  90:	ff11 0c12 	vqrdmlsh.s16	d0, d1, d2
+  94:	ff12 0c54 	vqrdmlsh.s16	q0, q1, q2
+  98:	ff21 0c12 	vqrdmlsh.s32	d0, d1, d2
+  9c:	ff22 0c54 	vqrdmlsh.s32	q0, q1, q2
+  a0:	ef91 0e42 	vqrdmlah.s16	d0, d1, d2\[0\]
+  a4:	ef91 0e4a 	vqrdmlah.s16	d0, d1, d2\[1\]
+  a8:	ef91 0e62 	vqrdmlah.s16	d0, d1, d2\[2\]
+  ac:	ef91 0e6a 	vqrdmlah.s16	d0, d1, d2\[3\]
+  b0:	ff92 0e42 	vqrdmlah.s16	q0, q1, d2\[0\]
+  b4:	ff92 0e4a 	vqrdmlah.s16	q0, q1, d2\[1\]
+  b8:	ff92 0e62 	vqrdmlah.s16	q0, q1, d2\[2\]
+  bc:	ff92 0e6a 	vqrdmlah.s16	q0, q1, d2\[3\]
+  c0:	efa1 0e42 	vqrdmlah.s32	d0, d1, d2\[0\]
+  c4:	efa1 0e62 	vqrdmlah.s32	d0, d1, d2\[1\]
+  c8:	ffa2 0e42 	vqrdmlah.s32	q0, q1, d2\[0\]
+  cc:	ffa2 0e62 	vqrdmlah.s32	q0, q1, d2\[1\]
+  d0:	ef91 0f42 	vqrdmlsh.s16	d0, d1, d2\[0\]
+  d4:	ef91 0f4a 	vqrdmlsh.s16	d0, d1, d2\[1\]
+  d8:	ef91 0f62 	vqrdmlsh.s16	d0, d1, d2\[2\]
+  dc:	ef91 0f6a 	vqrdmlsh.s16	d0, d1, d2\[3\]
+  e0:	ff92 0f42 	vqrdmlsh.s16	q0, q1, d2\[0\]
+  e4:	ff92 0f4a 	vqrdmlsh.s16	q0, q1, d2\[1\]
+  e8:	ff92 0f62 	vqrdmlsh.s16	q0, q1, d2\[2\]
+  ec:	ff92 0f6a 	vqrdmlsh.s16	q0, q1, d2\[3\]
+  f0:	efa1 0f42 	vqrdmlsh.s32	d0, d1, d2\[0\]
+  f4:	efa1 0f62 	vqrdmlsh.s32	d0, d1, d2\[1\]
+  f8:	ffa2 0f42 	vqrdmlsh.s32	q0, q1, d2\[0\]
+  fc:	ffa2 0f62 	vqrdmlsh.s32	q0, q1, d2\[1\]
+
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d b/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..4b7783ad509fd0e3beab0aa774c14f5dfd1fd274
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d
@@ -0,0 +1,249 @@ 
+#as: -march=armv8.2-a+fp16fml -mthumb
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc21 0810 	vfmal.f16	d0, s2, s0
+.*:	fe00 2810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca1 0810 	vfmsl.f16	d0, s2, s0
+.*:	fe10 2818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc21 0814 	vfmal.f16	d0, s2, s8
+.*:	fe00 2814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca1 0814 	vfmsl.f16	d0, s2, s8
+.*:	fe10 281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc21 0837 	vfmal.f16	d0, s2, s15
+.*:	fe00 2837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca1 0837 	vfmsl.f16	d0, s2, s15
+.*:	fe10 283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc27 0890 	vfmal.f16	d0, s15, s0
+.*:	fe00 f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca7 0890 	vfmsl.f16	d0, s15, s0
+.*:	fe10 f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc27 0894 	vfmal.f16	d0, s15, s8
+.*:	fe00 f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca7 0894 	vfmsl.f16	d0, s15, s8
+.*:	fe10 f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc27 08b7 	vfmal.f16	d0, s15, s15
+.*:	fe00 f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca7 08b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10 f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f 0810 	vfmal.f16	d0, s30, s0
+.*:	fe40 e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf 0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50 e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f 0814 	vfmal.f16	d0, s30, s8
+.*:	fe40 e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf 0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50 e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f 0837 	vfmal.f16	d0, s30, s15
+.*:	fe40 e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf 0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50 e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc21 7810 	vfmal.f16	d7, s2, s0
+.*:	fe03 2890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca1 7810 	vfmsl.f16	d7, s2, s0
+.*:	fe13 2898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc21 7814 	vfmal.f16	d7, s2, s8
+.*:	fe03 2894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca1 7814 	vfmsl.f16	d7, s2, s8
+.*:	fe13 289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc21 7837 	vfmal.f16	d7, s2, s15
+.*:	fe03 28b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca1 7837 	vfmsl.f16	d7, s2, s15
+.*:	fe13 28bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc27 7890 	vfmal.f16	d7, s15, s0
+.*:	fe03 f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca7 7890 	vfmsl.f16	d7, s15, s0
+.*:	fe13 f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc27 7894 	vfmal.f16	d7, s15, s8
+.*:	fe03 f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca7 7894 	vfmsl.f16	d7, s15, s8
+.*:	fe13 f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc27 78b7 	vfmal.f16	d7, s15, s15
+.*:	fe03 f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca7 78b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13 f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f 7810 	vfmal.f16	d7, s30, s0
+.*:	fe43 e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf 7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53 e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f 7814 	vfmal.f16	d7, s30, s8
+.*:	fe43 e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf 7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53 e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f 7837 	vfmal.f16	d7, s30, s15
+.*:	fe43 e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf 7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53 e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc61 0810 	vfmal.f16	d16, s2, s0
+.*:	fe08 2810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce1 0810 	vfmsl.f16	d16, s2, s0
+.*:	fe18 2818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc61 0814 	vfmal.f16	d16, s2, s8
+.*:	fe08 2814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce1 0814 	vfmsl.f16	d16, s2, s8
+.*:	fe18 281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc61 0837 	vfmal.f16	d16, s2, s15
+.*:	fe08 2837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce1 0837 	vfmsl.f16	d16, s2, s15
+.*:	fe18 283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc67 0890 	vfmal.f16	d16, s15, s0
+.*:	fe08 f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce7 0890 	vfmsl.f16	d16, s15, s0
+.*:	fe18 f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc67 0894 	vfmal.f16	d16, s15, s8
+.*:	fe08 f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce7 0894 	vfmsl.f16	d16, s15, s8
+.*:	fe18 f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc67 08b7 	vfmal.f16	d16, s15, s15
+.*:	fe08 f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce7 08b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18 f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f 0810 	vfmal.f16	d16, s30, s0
+.*:	fe48 e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef 0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58 e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f 0814 	vfmal.f16	d16, s30, s8
+.*:	fe48 e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef 0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58 e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f 0837 	vfmal.f16	d16, s30, s15
+.*:	fe48 e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef 0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58 e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61 f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f 2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1 f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f 2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61 f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f 2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1 f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f 289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61 f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f 28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1 f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f 28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67 f890 	vfmal.f16	d31, s15, s0
+.*:	fe0f f890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7 f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1f f898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67 f894 	vfmal.f16	d31, s15, s8
+.*:	fe0f f894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7 f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1f f89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67 f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0f f8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7 f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1f f8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6f f810 	vfmal.f16	d31, s30, s0
+.*:	fe4f e890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fcef f810 	vfmsl.f16	d31, s30, s0
+.*:	fe5f e898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6f f814 	vfmal.f16	d31, s30, s8
+.*:	fe4f e894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fcef f814 	vfmsl.f16	d31, s30, s8
+.*:	fe5f e89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6f f837 	vfmal.f16	d31, s30, s15
+.*:	fe4f e8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fcef f837 	vfmsl.f16	d31, s30, s15
+.*:	fe5f e8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc20 4850 	vfmal.f16	q2, d0, d0
+.*:	fe02 0850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca0 4850 	vfmsl.f16	q2, d0, d0
+.*:	fe12 0878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc20 4857 	vfmal.f16	q2, d0, d7
+.*:	fe02 0857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca0 4857 	vfmsl.f16	q2, d0, d7
+.*:	fe12 087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc20 6850 	vfmal.f16	q3, d0, d0
+.*:	fe03 0850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca0 6850 	vfmsl.f16	q3, d0, d0
+.*:	fe13 0878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc20 6857 	vfmal.f16	q3, d0, d7
+.*:	fe03 0857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca0 6857 	vfmsl.f16	q3, d0, d7
+.*:	fe13 087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60 a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d 0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0 a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d 0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60 a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d 0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0 a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d 087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc21 4850 	vfmal.f16	q2, d1, d0
+.*:	fe02 2850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca1 4850 	vfmsl.f16	q2, d1, d0
+.*:	fe12 2878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc21 4857 	vfmal.f16	q2, d1, d7
+.*:	fe02 2857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca1 4857 	vfmsl.f16	q2, d1, d7
+.*:	fe12 287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc21 6850 	vfmal.f16	q3, d1, d0
+.*:	fe03 2850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca1 6850 	vfmsl.f16	q3, d1, d0
+.*:	fe13 2878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc21 6857 	vfmal.f16	q3, d1, d7
+.*:	fe03 2857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca1 6857 	vfmsl.f16	q3, d1, d7
+.*:	fe13 287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61 a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d 2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1 a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d 2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61 a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d 2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1 a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d 287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc26 4850 	vfmal.f16	q2, d6, d0
+.*:	fe02 c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca6 4850 	vfmsl.f16	q2, d6, d0
+.*:	fe12 c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc26 4857 	vfmal.f16	q2, d6, d7
+.*:	fe02 c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca6 4857 	vfmsl.f16	q2, d6, d7
+.*:	fe12 c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc26 6850 	vfmal.f16	q3, d6, d0
+.*:	fe03 c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca6 6850 	vfmsl.f16	q3, d6, d0
+.*:	fe13 c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc26 6857 	vfmal.f16	q3, d6, d7
+.*:	fe03 c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca6 6857 	vfmsl.f16	q3, d6, d7
+.*:	fe13 c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66 a850 	vfmal.f16	q13, d6, d0
+.*:	fe0d c850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6 a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1d c878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66 a857 	vfmal.f16	q13, d6, d7
+.*:	fe0d c857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6 a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1d c87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f 4850 	vfmal.f16	q2, d15, d0
+.*:	fe42 e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf 4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52 e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f 4857 	vfmal.f16	q2, d15, d7
+.*:	fe42 e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf 4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52 e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f 6850 	vfmal.f16	q3, d15, d0
+.*:	fe43 e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf 6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53 e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f 6857 	vfmal.f16	q3, d15, d7
+.*:	fe43 e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf 6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53 e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6f a850 	vfmal.f16	q13, d15, d0
+.*:	fe4d e850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcef a850 	vfmsl.f16	q13, d15, d0
+.*:	fe5d e878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6f a857 	vfmal.f16	q13, d15, d7
+.*:	fe4d e857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcef a857 	vfmsl.f16	q13, d15, d7
+.*:	fe5d e87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d b/gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..836ecfc5280e1ca326fcd4dc7a3edd6ee1df3023
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d
@@ -0,0 +1,249 @@ 
+#as: -march=armv8.2-a+fp16fml
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc210810 	vfmal.f16	d0, s2, s0
+.*:	fe002810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca10810 	vfmsl.f16	d0, s2, s0
+.*:	fe102818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc210814 	vfmal.f16	d0, s2, s8
+.*:	fe002814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca10814 	vfmsl.f16	d0, s2, s8
+.*:	fe10281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc210837 	vfmal.f16	d0, s2, s15
+.*:	fe002837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca10837 	vfmsl.f16	d0, s2, s15
+.*:	fe10283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc270890 	vfmal.f16	d0, s15, s0
+.*:	fe00f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca70890 	vfmsl.f16	d0, s15, s0
+.*:	fe10f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc270894 	vfmal.f16	d0, s15, s8
+.*:	fe00f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca70894 	vfmsl.f16	d0, s15, s8
+.*:	fe10f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc2708b7 	vfmal.f16	d0, s15, s15
+.*:	fe00f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca708b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f0810 	vfmal.f16	d0, s30, s0
+.*:	fe40e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f0814 	vfmal.f16	d0, s30, s8
+.*:	fe40e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f0837 	vfmal.f16	d0, s30, s15
+.*:	fe40e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc217810 	vfmal.f16	d7, s2, s0
+.*:	fe032890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca17810 	vfmsl.f16	d7, s2, s0
+.*:	fe132898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc217814 	vfmal.f16	d7, s2, s8
+.*:	fe032894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca17814 	vfmsl.f16	d7, s2, s8
+.*:	fe13289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc217837 	vfmal.f16	d7, s2, s15
+.*:	fe0328b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca17837 	vfmsl.f16	d7, s2, s15
+.*:	fe1328bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc277890 	vfmal.f16	d7, s15, s0
+.*:	fe03f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca77890 	vfmsl.f16	d7, s15, s0
+.*:	fe13f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc277894 	vfmal.f16	d7, s15, s8
+.*:	fe03f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca77894 	vfmsl.f16	d7, s15, s8
+.*:	fe13f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc2778b7 	vfmal.f16	d7, s15, s15
+.*:	fe03f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca778b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f7810 	vfmal.f16	d7, s30, s0
+.*:	fe43e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f7814 	vfmal.f16	d7, s30, s8
+.*:	fe43e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f7837 	vfmal.f16	d7, s30, s15
+.*:	fe43e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc610810 	vfmal.f16	d16, s2, s0
+.*:	fe082810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce10810 	vfmsl.f16	d16, s2, s0
+.*:	fe182818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc610814 	vfmal.f16	d16, s2, s8
+.*:	fe082814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce10814 	vfmsl.f16	d16, s2, s8
+.*:	fe18281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc610837 	vfmal.f16	d16, s2, s15
+.*:	fe082837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce10837 	vfmsl.f16	d16, s2, s15
+.*:	fe18283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc670890 	vfmal.f16	d16, s15, s0
+.*:	fe08f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce70890 	vfmsl.f16	d16, s15, s0
+.*:	fe18f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc670894 	vfmal.f16	d16, s15, s8
+.*:	fe08f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce70894 	vfmsl.f16	d16, s15, s8
+.*:	fe18f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc6708b7 	vfmal.f16	d16, s15, s15
+.*:	fe08f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce708b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f0810 	vfmal.f16	d16, s30, s0
+.*:	fe48e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f0814 	vfmal.f16	d16, s30, s8
+.*:	fe48e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f0837 	vfmal.f16	d16, s30, s15
+.*:	fe48e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67f890 	vfmal.f16	d31, s15, s0
+.*:	fe0ff890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1ff898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67f894 	vfmal.f16	d31, s15, s8
+.*:	fe0ff894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1ff89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0ff8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1ff8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6ff810 	vfmal.f16	d31, s30, s0
+.*:	fe4fe890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fceff810 	vfmsl.f16	d31, s30, s0
+.*:	fe5fe898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6ff814 	vfmal.f16	d31, s30, s8
+.*:	fe4fe894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fceff814 	vfmsl.f16	d31, s30, s8
+.*:	fe5fe89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6ff837 	vfmal.f16	d31, s30, s15
+.*:	fe4fe8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fceff837 	vfmsl.f16	d31, s30, s15
+.*:	fe5fe8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc204850 	vfmal.f16	q2, d0, d0
+.*:	fe020850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca04850 	vfmsl.f16	q2, d0, d0
+.*:	fe120878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc204857 	vfmal.f16	q2, d0, d7
+.*:	fe020857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca04857 	vfmsl.f16	q2, d0, d7
+.*:	fe12087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc206850 	vfmal.f16	q3, d0, d0
+.*:	fe030850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca06850 	vfmsl.f16	q3, d0, d0
+.*:	fe130878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc206857 	vfmal.f16	q3, d0, d7
+.*:	fe030857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca06857 	vfmsl.f16	q3, d0, d7
+.*:	fe13087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc214850 	vfmal.f16	q2, d1, d0
+.*:	fe022850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca14850 	vfmsl.f16	q2, d1, d0
+.*:	fe122878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc214857 	vfmal.f16	q2, d1, d7
+.*:	fe022857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca14857 	vfmsl.f16	q2, d1, d7
+.*:	fe12287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc216850 	vfmal.f16	q3, d1, d0
+.*:	fe032850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca16850 	vfmsl.f16	q3, d1, d0
+.*:	fe132878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc216857 	vfmal.f16	q3, d1, d7
+.*:	fe032857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca16857 	vfmsl.f16	q3, d1, d7
+.*:	fe13287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc264850 	vfmal.f16	q2, d6, d0
+.*:	fe02c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca64850 	vfmsl.f16	q2, d6, d0
+.*:	fe12c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc264857 	vfmal.f16	q2, d6, d7
+.*:	fe02c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca64857 	vfmsl.f16	q2, d6, d7
+.*:	fe12c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc266850 	vfmal.f16	q3, d6, d0
+.*:	fe03c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca66850 	vfmsl.f16	q3, d6, d0
+.*:	fe13c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc266857 	vfmal.f16	q3, d6, d7
+.*:	fe03c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca66857 	vfmsl.f16	q3, d6, d7
+.*:	fe13c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66a850 	vfmal.f16	q13, d6, d0
+.*:	fe0dc850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1dc878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66a857 	vfmal.f16	q13, d6, d7
+.*:	fe0dc857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1dc87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f4850 	vfmal.f16	q2, d15, d0
+.*:	fe42e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f4857 	vfmal.f16	q2, d15, d7
+.*:	fe42e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f6850 	vfmal.f16	q3, d15, d0
+.*:	fe43e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f6857 	vfmal.f16	q3, d15, d7
+.*:	fe43e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6fa850 	vfmal.f16	q13, d15, d0
+.*:	fe4de850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcefa850 	vfmsl.f16	q13, d15, d0
+.*:	fe5de878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6fa857 	vfmal.f16	q13, d15, d7
+.*:	fe4de857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcefa857 	vfmsl.f16	q13, d15, d7
+.*:	fe5de87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d b/gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..3b1e299649641e279dff47c7a8ef1ced32d7d082
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d
@@ -0,0 +1,3 @@ 
+#as: -march=armv8.3-a+simd
+#source: armv8_3-a-fp-bad.s
+#error_output: armv8_3-a-fp-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-ext.d b/gas/testsuite/gas/arm/armv8_3-a-fp-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..81710e3549328264becceb86026fdb0c32c1a3e1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-ext.d
@@ -0,0 +1,16 @@ 
+#as: -march=armv8.3-a+simd
+#source: armv8_3-a-fp.s
+#objdump: -dr
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+   [0-9a-f]+:	eef90bc7 	vjcvt.s32.f64	s1, d7
+   [0-9a-f]+:	eef90bc7 	vjcvt.s32.f64	s1, d7
+
+[0-9a-f]+ <.*>:
+   [0-9a-f]+:	eef9 0bc7 	vjcvt.s32.f64	s1, d7
+
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d b/gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..80716b58c29df9751dc58f78d1de626a1e2ba638
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d
@@ -0,0 +1,249 @@ 
+#as: -march=armv8.3-a+fp16fml
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc210810 	vfmal.f16	d0, s2, s0
+.*:	fe002810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca10810 	vfmsl.f16	d0, s2, s0
+.*:	fe102818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc210814 	vfmal.f16	d0, s2, s8
+.*:	fe002814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca10814 	vfmsl.f16	d0, s2, s8
+.*:	fe10281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc210837 	vfmal.f16	d0, s2, s15
+.*:	fe002837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca10837 	vfmsl.f16	d0, s2, s15
+.*:	fe10283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc270890 	vfmal.f16	d0, s15, s0
+.*:	fe00f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca70890 	vfmsl.f16	d0, s15, s0
+.*:	fe10f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc270894 	vfmal.f16	d0, s15, s8
+.*:	fe00f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca70894 	vfmsl.f16	d0, s15, s8
+.*:	fe10f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc2708b7 	vfmal.f16	d0, s15, s15
+.*:	fe00f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca708b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f0810 	vfmal.f16	d0, s30, s0
+.*:	fe40e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f0814 	vfmal.f16	d0, s30, s8
+.*:	fe40e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f0837 	vfmal.f16	d0, s30, s15
+.*:	fe40e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc217810 	vfmal.f16	d7, s2, s0
+.*:	fe032890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca17810 	vfmsl.f16	d7, s2, s0
+.*:	fe132898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc217814 	vfmal.f16	d7, s2, s8
+.*:	fe032894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca17814 	vfmsl.f16	d7, s2, s8
+.*:	fe13289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc217837 	vfmal.f16	d7, s2, s15
+.*:	fe0328b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca17837 	vfmsl.f16	d7, s2, s15
+.*:	fe1328bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc277890 	vfmal.f16	d7, s15, s0
+.*:	fe03f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca77890 	vfmsl.f16	d7, s15, s0
+.*:	fe13f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc277894 	vfmal.f16	d7, s15, s8
+.*:	fe03f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca77894 	vfmsl.f16	d7, s15, s8
+.*:	fe13f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc2778b7 	vfmal.f16	d7, s15, s15
+.*:	fe03f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca778b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f7810 	vfmal.f16	d7, s30, s0
+.*:	fe43e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f7814 	vfmal.f16	d7, s30, s8
+.*:	fe43e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f7837 	vfmal.f16	d7, s30, s15
+.*:	fe43e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc610810 	vfmal.f16	d16, s2, s0
+.*:	fe082810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce10810 	vfmsl.f16	d16, s2, s0
+.*:	fe182818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc610814 	vfmal.f16	d16, s2, s8
+.*:	fe082814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce10814 	vfmsl.f16	d16, s2, s8
+.*:	fe18281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc610837 	vfmal.f16	d16, s2, s15
+.*:	fe082837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce10837 	vfmsl.f16	d16, s2, s15
+.*:	fe18283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc670890 	vfmal.f16	d16, s15, s0
+.*:	fe08f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce70890 	vfmsl.f16	d16, s15, s0
+.*:	fe18f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc670894 	vfmal.f16	d16, s15, s8
+.*:	fe08f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce70894 	vfmsl.f16	d16, s15, s8
+.*:	fe18f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc6708b7 	vfmal.f16	d16, s15, s15
+.*:	fe08f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce708b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f0810 	vfmal.f16	d16, s30, s0
+.*:	fe48e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f0814 	vfmal.f16	d16, s30, s8
+.*:	fe48e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f0837 	vfmal.f16	d16, s30, s15
+.*:	fe48e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67f890 	vfmal.f16	d31, s15, s0
+.*:	fe0ff890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1ff898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67f894 	vfmal.f16	d31, s15, s8
+.*:	fe0ff894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1ff89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0ff8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1ff8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6ff810 	vfmal.f16	d31, s30, s0
+.*:	fe4fe890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fceff810 	vfmsl.f16	d31, s30, s0
+.*:	fe5fe898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6ff814 	vfmal.f16	d31, s30, s8
+.*:	fe4fe894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fceff814 	vfmsl.f16	d31, s30, s8
+.*:	fe5fe89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6ff837 	vfmal.f16	d31, s30, s15
+.*:	fe4fe8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fceff837 	vfmsl.f16	d31, s30, s15
+.*:	fe5fe8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc204850 	vfmal.f16	q2, d0, d0
+.*:	fe020850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca04850 	vfmsl.f16	q2, d0, d0
+.*:	fe120878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc204857 	vfmal.f16	q2, d0, d7
+.*:	fe020857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca04857 	vfmsl.f16	q2, d0, d7
+.*:	fe12087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc206850 	vfmal.f16	q3, d0, d0
+.*:	fe030850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca06850 	vfmsl.f16	q3, d0, d0
+.*:	fe130878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc206857 	vfmal.f16	q3, d0, d7
+.*:	fe030857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca06857 	vfmsl.f16	q3, d0, d7
+.*:	fe13087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc214850 	vfmal.f16	q2, d1, d0
+.*:	fe022850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca14850 	vfmsl.f16	q2, d1, d0
+.*:	fe122878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc214857 	vfmal.f16	q2, d1, d7
+.*:	fe022857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca14857 	vfmsl.f16	q2, d1, d7
+.*:	fe12287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc216850 	vfmal.f16	q3, d1, d0
+.*:	fe032850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca16850 	vfmsl.f16	q3, d1, d0
+.*:	fe132878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc216857 	vfmal.f16	q3, d1, d7
+.*:	fe032857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca16857 	vfmsl.f16	q3, d1, d7
+.*:	fe13287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc264850 	vfmal.f16	q2, d6, d0
+.*:	fe02c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca64850 	vfmsl.f16	q2, d6, d0
+.*:	fe12c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc264857 	vfmal.f16	q2, d6, d7
+.*:	fe02c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca64857 	vfmsl.f16	q2, d6, d7
+.*:	fe12c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc266850 	vfmal.f16	q3, d6, d0
+.*:	fe03c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca66850 	vfmsl.f16	q3, d6, d0
+.*:	fe13c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc266857 	vfmal.f16	q3, d6, d7
+.*:	fe03c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca66857 	vfmsl.f16	q3, d6, d7
+.*:	fe13c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66a850 	vfmal.f16	q13, d6, d0
+.*:	fe0dc850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1dc878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66a857 	vfmal.f16	q13, d6, d7
+.*:	fe0dc857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1dc87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f4850 	vfmal.f16	q2, d15, d0
+.*:	fe42e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f4857 	vfmal.f16	q2, d15, d7
+.*:	fe42e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f6850 	vfmal.f16	q3, d15, d0
+.*:	fe43e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f6857 	vfmal.f16	q3, d15, d7
+.*:	fe43e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6fa850 	vfmal.f16	q13, d15, d0
+.*:	fe4de850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcefa850 	vfmsl.f16	q13, d15, d0
+.*:	fe5de878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6fa857 	vfmal.f16	q13, d15, d7
+.*:	fe4de857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcefa857 	vfmsl.f16	q13, d15, d7
+.*:	fe5de87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d b/gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..a21236771593247030a7e66ff186ad352c61f50a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d
@@ -0,0 +1,3 @@ 
+#as: -march=armv8.3-a+fp16
+#source: armv8_3-a-simd-bad.s
+#error_output: armv8_3-a-simd-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d b/gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..5746bbf814290c4eead5f15c7685a727cc1f5eb8
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d
@@ -0,0 +1,249 @@ 
+#as: -march=armv8.4-a+fp16
+#source: armv8_2-a-fp16.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc210810 	vfmal.f16	d0, s2, s0
+.*:	fe002810 	vfmal.f16	d2, s0, s0\[0\]
+.*:	fca10810 	vfmsl.f16	d0, s2, s0
+.*:	fe102818 	vfmsl.f16	d2, s0, s0\[1\]
+.*:	fc210814 	vfmal.f16	d0, s2, s8
+.*:	fe002814 	vfmal.f16	d2, s0, s8\[0\]
+.*:	fca10814 	vfmsl.f16	d0, s2, s8
+.*:	fe10281c 	vfmsl.f16	d2, s0, s8\[1\]
+.*:	fc210837 	vfmal.f16	d0, s2, s15
+.*:	fe002837 	vfmal.f16	d2, s0, s15\[0\]
+.*:	fca10837 	vfmsl.f16	d0, s2, s15
+.*:	fe10283f 	vfmsl.f16	d2, s0, s15\[1\]
+.*:	fc270890 	vfmal.f16	d0, s15, s0
+.*:	fe00f810 	vfmal.f16	d15, s0, s0\[0\]
+.*:	fca70890 	vfmsl.f16	d0, s15, s0
+.*:	fe10f818 	vfmsl.f16	d15, s0, s0\[1\]
+.*:	fc270894 	vfmal.f16	d0, s15, s8
+.*:	fe00f814 	vfmal.f16	d15, s0, s8\[0\]
+.*:	fca70894 	vfmsl.f16	d0, s15, s8
+.*:	fe10f81c 	vfmsl.f16	d15, s0, s8\[1\]
+.*:	fc2708b7 	vfmal.f16	d0, s15, s15
+.*:	fe00f837 	vfmal.f16	d15, s0, s15\[0\]
+.*:	fca708b7 	vfmsl.f16	d0, s15, s15
+.*:	fe10f83f 	vfmsl.f16	d15, s0, s15\[1\]
+.*:	fc2f0810 	vfmal.f16	d0, s30, s0
+.*:	fe40e810 	vfmal.f16	d30, s0, s0\[0\]
+.*:	fcaf0810 	vfmsl.f16	d0, s30, s0
+.*:	fe50e818 	vfmsl.f16	d30, s0, s0\[1\]
+.*:	fc2f0814 	vfmal.f16	d0, s30, s8
+.*:	fe40e814 	vfmal.f16	d30, s0, s8\[0\]
+.*:	fcaf0814 	vfmsl.f16	d0, s30, s8
+.*:	fe50e81c 	vfmsl.f16	d30, s0, s8\[1\]
+.*:	fc2f0837 	vfmal.f16	d0, s30, s15
+.*:	fe40e837 	vfmal.f16	d30, s0, s15\[0\]
+.*:	fcaf0837 	vfmsl.f16	d0, s30, s15
+.*:	fe50e83f 	vfmsl.f16	d30, s0, s15\[1\]
+.*:	fc217810 	vfmal.f16	d7, s2, s0
+.*:	fe032890 	vfmal.f16	d2, s7, s0\[0\]
+.*:	fca17810 	vfmsl.f16	d7, s2, s0
+.*:	fe132898 	vfmsl.f16	d2, s7, s0\[1\]
+.*:	fc217814 	vfmal.f16	d7, s2, s8
+.*:	fe032894 	vfmal.f16	d2, s7, s8\[0\]
+.*:	fca17814 	vfmsl.f16	d7, s2, s8
+.*:	fe13289c 	vfmsl.f16	d2, s7, s8\[1\]
+.*:	fc217837 	vfmal.f16	d7, s2, s15
+.*:	fe0328b7 	vfmal.f16	d2, s7, s15\[0\]
+.*:	fca17837 	vfmsl.f16	d7, s2, s15
+.*:	fe1328bf 	vfmsl.f16	d2, s7, s15\[1\]
+.*:	fc277890 	vfmal.f16	d7, s15, s0
+.*:	fe03f890 	vfmal.f16	d15, s7, s0\[0\]
+.*:	fca77890 	vfmsl.f16	d7, s15, s0
+.*:	fe13f898 	vfmsl.f16	d15, s7, s0\[1\]
+.*:	fc277894 	vfmal.f16	d7, s15, s8
+.*:	fe03f894 	vfmal.f16	d15, s7, s8\[0\]
+.*:	fca77894 	vfmsl.f16	d7, s15, s8
+.*:	fe13f89c 	vfmsl.f16	d15, s7, s8\[1\]
+.*:	fc2778b7 	vfmal.f16	d7, s15, s15
+.*:	fe03f8b7 	vfmal.f16	d15, s7, s15\[0\]
+.*:	fca778b7 	vfmsl.f16	d7, s15, s15
+.*:	fe13f8bf 	vfmsl.f16	d15, s7, s15\[1\]
+.*:	fc2f7810 	vfmal.f16	d7, s30, s0
+.*:	fe43e890 	vfmal.f16	d30, s7, s0\[0\]
+.*:	fcaf7810 	vfmsl.f16	d7, s30, s0
+.*:	fe53e898 	vfmsl.f16	d30, s7, s0\[1\]
+.*:	fc2f7814 	vfmal.f16	d7, s30, s8
+.*:	fe43e894 	vfmal.f16	d30, s7, s8\[0\]
+.*:	fcaf7814 	vfmsl.f16	d7, s30, s8
+.*:	fe53e89c 	vfmsl.f16	d30, s7, s8\[1\]
+.*:	fc2f7837 	vfmal.f16	d7, s30, s15
+.*:	fe43e8b7 	vfmal.f16	d30, s7, s15\[0\]
+.*:	fcaf7837 	vfmsl.f16	d7, s30, s15
+.*:	fe53e8bf 	vfmsl.f16	d30, s7, s15\[1\]
+.*:	fc610810 	vfmal.f16	d16, s2, s0
+.*:	fe082810 	vfmal.f16	d2, s16, s0\[0\]
+.*:	fce10810 	vfmsl.f16	d16, s2, s0
+.*:	fe182818 	vfmsl.f16	d2, s16, s0\[1\]
+.*:	fc610814 	vfmal.f16	d16, s2, s8
+.*:	fe082814 	vfmal.f16	d2, s16, s8\[0\]
+.*:	fce10814 	vfmsl.f16	d16, s2, s8
+.*:	fe18281c 	vfmsl.f16	d2, s16, s8\[1\]
+.*:	fc610837 	vfmal.f16	d16, s2, s15
+.*:	fe082837 	vfmal.f16	d2, s16, s15\[0\]
+.*:	fce10837 	vfmsl.f16	d16, s2, s15
+.*:	fe18283f 	vfmsl.f16	d2, s16, s15\[1\]
+.*:	fc670890 	vfmal.f16	d16, s15, s0
+.*:	fe08f810 	vfmal.f16	d15, s16, s0\[0\]
+.*:	fce70890 	vfmsl.f16	d16, s15, s0
+.*:	fe18f818 	vfmsl.f16	d15, s16, s0\[1\]
+.*:	fc670894 	vfmal.f16	d16, s15, s8
+.*:	fe08f814 	vfmal.f16	d15, s16, s8\[0\]
+.*:	fce70894 	vfmsl.f16	d16, s15, s8
+.*:	fe18f81c 	vfmsl.f16	d15, s16, s8\[1\]
+.*:	fc6708b7 	vfmal.f16	d16, s15, s15
+.*:	fe08f837 	vfmal.f16	d15, s16, s15\[0\]
+.*:	fce708b7 	vfmsl.f16	d16, s15, s15
+.*:	fe18f83f 	vfmsl.f16	d15, s16, s15\[1\]
+.*:	fc6f0810 	vfmal.f16	d16, s30, s0
+.*:	fe48e810 	vfmal.f16	d30, s16, s0\[0\]
+.*:	fcef0810 	vfmsl.f16	d16, s30, s0
+.*:	fe58e818 	vfmsl.f16	d30, s16, s0\[1\]
+.*:	fc6f0814 	vfmal.f16	d16, s30, s8
+.*:	fe48e814 	vfmal.f16	d30, s16, s8\[0\]
+.*:	fcef0814 	vfmsl.f16	d16, s30, s8
+.*:	fe58e81c 	vfmsl.f16	d30, s16, s8\[1\]
+.*:	fc6f0837 	vfmal.f16	d16, s30, s15
+.*:	fe48e837 	vfmal.f16	d30, s16, s15\[0\]
+.*:	fcef0837 	vfmsl.f16	d16, s30, s15
+.*:	fe58e83f 	vfmsl.f16	d30, s16, s15\[1\]
+.*:	fc61f810 	vfmal.f16	d31, s2, s0
+.*:	fe0f2890 	vfmal.f16	d2, s31, s0\[0\]
+.*:	fce1f810 	vfmsl.f16	d31, s2, s0
+.*:	fe1f2898 	vfmsl.f16	d2, s31, s0\[1\]
+.*:	fc61f814 	vfmal.f16	d31, s2, s8
+.*:	fe0f2894 	vfmal.f16	d2, s31, s8\[0\]
+.*:	fce1f814 	vfmsl.f16	d31, s2, s8
+.*:	fe1f289c 	vfmsl.f16	d2, s31, s8\[1\]
+.*:	fc61f837 	vfmal.f16	d31, s2, s15
+.*:	fe0f28b7 	vfmal.f16	d2, s31, s15\[0\]
+.*:	fce1f837 	vfmsl.f16	d31, s2, s15
+.*:	fe1f28bf 	vfmsl.f16	d2, s31, s15\[1\]
+.*:	fc67f890 	vfmal.f16	d31, s15, s0
+.*:	fe0ff890 	vfmal.f16	d15, s31, s0\[0\]
+.*:	fce7f890 	vfmsl.f16	d31, s15, s0
+.*:	fe1ff898 	vfmsl.f16	d15, s31, s0\[1\]
+.*:	fc67f894 	vfmal.f16	d31, s15, s8
+.*:	fe0ff894 	vfmal.f16	d15, s31, s8\[0\]
+.*:	fce7f894 	vfmsl.f16	d31, s15, s8
+.*:	fe1ff89c 	vfmsl.f16	d15, s31, s8\[1\]
+.*:	fc67f8b7 	vfmal.f16	d31, s15, s15
+.*:	fe0ff8b7 	vfmal.f16	d15, s31, s15\[0\]
+.*:	fce7f8b7 	vfmsl.f16	d31, s15, s15
+.*:	fe1ff8bf 	vfmsl.f16	d15, s31, s15\[1\]
+.*:	fc6ff810 	vfmal.f16	d31, s30, s0
+.*:	fe4fe890 	vfmal.f16	d30, s31, s0\[0\]
+.*:	fceff810 	vfmsl.f16	d31, s30, s0
+.*:	fe5fe898 	vfmsl.f16	d30, s31, s0\[1\]
+.*:	fc6ff814 	vfmal.f16	d31, s30, s8
+.*:	fe4fe894 	vfmal.f16	d30, s31, s8\[0\]
+.*:	fceff814 	vfmsl.f16	d31, s30, s8
+.*:	fe5fe89c 	vfmsl.f16	d30, s31, s8\[1\]
+.*:	fc6ff837 	vfmal.f16	d31, s30, s15
+.*:	fe4fe8b7 	vfmal.f16	d30, s31, s15\[0\]
+.*:	fceff837 	vfmsl.f16	d31, s30, s15
+.*:	fe5fe8bf 	vfmsl.f16	d30, s31, s15\[1\]
+.*:	fc204850 	vfmal.f16	q2, d0, d0
+.*:	fe020850 	vfmal.f16	q0, d2, d0\[0\]
+.*:	fca04850 	vfmsl.f16	q2, d0, d0
+.*:	fe120878 	vfmsl.f16	q0, d2, d0\[3\]
+.*:	fc204857 	vfmal.f16	q2, d0, d7
+.*:	fe020857 	vfmal.f16	q0, d2, d7\[0\]
+.*:	fca04857 	vfmsl.f16	q2, d0, d7
+.*:	fe12087f 	vfmsl.f16	q0, d2, d7\[3\]
+.*:	fc206850 	vfmal.f16	q3, d0, d0
+.*:	fe030850 	vfmal.f16	q0, d3, d0\[0\]
+.*:	fca06850 	vfmsl.f16	q3, d0, d0
+.*:	fe130878 	vfmsl.f16	q0, d3, d0\[3\]
+.*:	fc206857 	vfmal.f16	q3, d0, d7
+.*:	fe030857 	vfmal.f16	q0, d3, d7\[0\]
+.*:	fca06857 	vfmsl.f16	q3, d0, d7
+.*:	fe13087f 	vfmsl.f16	q0, d3, d7\[3\]
+.*:	fc60a850 	vfmal.f16	q13, d0, d0
+.*:	fe0d0850 	vfmal.f16	q0, d13, d0\[0\]
+.*:	fce0a850 	vfmsl.f16	q13, d0, d0
+.*:	fe1d0878 	vfmsl.f16	q0, d13, d0\[3\]
+.*:	fc60a857 	vfmal.f16	q13, d0, d7
+.*:	fe0d0857 	vfmal.f16	q0, d13, d7\[0\]
+.*:	fce0a857 	vfmsl.f16	q13, d0, d7
+.*:	fe1d087f 	vfmsl.f16	q0, d13, d7\[3\]
+.*:	fc214850 	vfmal.f16	q2, d1, d0
+.*:	fe022850 	vfmal.f16	q1, d2, d0\[0\]
+.*:	fca14850 	vfmsl.f16	q2, d1, d0
+.*:	fe122878 	vfmsl.f16	q1, d2, d0\[3\]
+.*:	fc214857 	vfmal.f16	q2, d1, d7
+.*:	fe022857 	vfmal.f16	q1, d2, d7\[0\]
+.*:	fca14857 	vfmsl.f16	q2, d1, d7
+.*:	fe12287f 	vfmsl.f16	q1, d2, d7\[3\]
+.*:	fc216850 	vfmal.f16	q3, d1, d0
+.*:	fe032850 	vfmal.f16	q1, d3, d0\[0\]
+.*:	fca16850 	vfmsl.f16	q3, d1, d0
+.*:	fe132878 	vfmsl.f16	q1, d3, d0\[3\]
+.*:	fc216857 	vfmal.f16	q3, d1, d7
+.*:	fe032857 	vfmal.f16	q1, d3, d7\[0\]
+.*:	fca16857 	vfmsl.f16	q3, d1, d7
+.*:	fe13287f 	vfmsl.f16	q1, d3, d7\[3\]
+.*:	fc61a850 	vfmal.f16	q13, d1, d0
+.*:	fe0d2850 	vfmal.f16	q1, d13, d0\[0\]
+.*:	fce1a850 	vfmsl.f16	q13, d1, d0
+.*:	fe1d2878 	vfmsl.f16	q1, d13, d0\[3\]
+.*:	fc61a857 	vfmal.f16	q13, d1, d7
+.*:	fe0d2857 	vfmal.f16	q1, d13, d7\[0\]
+.*:	fce1a857 	vfmsl.f16	q13, d1, d7
+.*:	fe1d287f 	vfmsl.f16	q1, d13, d7\[3\]
+.*:	fc264850 	vfmal.f16	q2, d6, d0
+.*:	fe02c850 	vfmal.f16	q6, d2, d0\[0\]
+.*:	fca64850 	vfmsl.f16	q2, d6, d0
+.*:	fe12c878 	vfmsl.f16	q6, d2, d0\[3\]
+.*:	fc264857 	vfmal.f16	q2, d6, d7
+.*:	fe02c857 	vfmal.f16	q6, d2, d7\[0\]
+.*:	fca64857 	vfmsl.f16	q2, d6, d7
+.*:	fe12c87f 	vfmsl.f16	q6, d2, d7\[3\]
+.*:	fc266850 	vfmal.f16	q3, d6, d0
+.*:	fe03c850 	vfmal.f16	q6, d3, d0\[0\]
+.*:	fca66850 	vfmsl.f16	q3, d6, d0
+.*:	fe13c878 	vfmsl.f16	q6, d3, d0\[3\]
+.*:	fc266857 	vfmal.f16	q3, d6, d7
+.*:	fe03c857 	vfmal.f16	q6, d3, d7\[0\]
+.*:	fca66857 	vfmsl.f16	q3, d6, d7
+.*:	fe13c87f 	vfmsl.f16	q6, d3, d7\[3\]
+.*:	fc66a850 	vfmal.f16	q13, d6, d0
+.*:	fe0dc850 	vfmal.f16	q6, d13, d0\[0\]
+.*:	fce6a850 	vfmsl.f16	q13, d6, d0
+.*:	fe1dc878 	vfmsl.f16	q6, d13, d0\[3\]
+.*:	fc66a857 	vfmal.f16	q13, d6, d7
+.*:	fe0dc857 	vfmal.f16	q6, d13, d7\[0\]
+.*:	fce6a857 	vfmsl.f16	q13, d6, d7
+.*:	fe1dc87f 	vfmsl.f16	q6, d13, d7\[3\]
+.*:	fc2f4850 	vfmal.f16	q2, d15, d0
+.*:	fe42e850 	vfmal.f16	q15, d2, d0\[0\]
+.*:	fcaf4850 	vfmsl.f16	q2, d15, d0
+.*:	fe52e878 	vfmsl.f16	q15, d2, d0\[3\]
+.*:	fc2f4857 	vfmal.f16	q2, d15, d7
+.*:	fe42e857 	vfmal.f16	q15, d2, d7\[0\]
+.*:	fcaf4857 	vfmsl.f16	q2, d15, d7
+.*:	fe52e87f 	vfmsl.f16	q15, d2, d7\[3\]
+.*:	fc2f6850 	vfmal.f16	q3, d15, d0
+.*:	fe43e850 	vfmal.f16	q15, d3, d0\[0\]
+.*:	fcaf6850 	vfmsl.f16	q3, d15, d0
+.*:	fe53e878 	vfmsl.f16	q15, d3, d0\[3\]
+.*:	fc2f6857 	vfmal.f16	q3, d15, d7
+.*:	fe43e857 	vfmal.f16	q15, d3, d7\[0\]
+.*:	fcaf6857 	vfmsl.f16	q3, d15, d7
+.*:	fe53e87f 	vfmsl.f16	q15, d3, d7\[3\]
+.*:	fc6fa850 	vfmal.f16	q13, d15, d0
+.*:	fe4de850 	vfmal.f16	q15, d13, d0\[0\]
+.*:	fcefa850 	vfmsl.f16	q13, d15, d0
+.*:	fe5de878 	vfmsl.f16	q15, d13, d0\[3\]
+.*:	fc6fa857 	vfmal.f16	q13, d15, d7
+.*:	fe4de857 	vfmal.f16	q15, d13, d7\[0\]
+.*:	fcefa857 	vfmsl.f16	q13, d15, d7
+.*:	fe5de87f 	vfmsl.f16	q15, d13, d7\[3\]
diff --git a/gas/testsuite/gas/arm/armv8m.main+fp.d b/gas/testsuite/gas/arm/armv8m.main+fp.d
new file mode 100644
index 0000000000000000000000000000000000000000..cc318e23f7434ca8099aaae34d7b7d4dfaf76202
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8m.main+fp.d
@@ -0,0 +1,32 @@ 
+#name: Valid armv8-m.main+fp
+#as: -march=armv8-m.main+fp
+#source: fpv5-sp-d16.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
diff --git a/gas/testsuite/gas/arm/armv8m.main+fp.dp.d b/gas/testsuite/gas/arm/armv8m.main+fp.dp.d
new file mode 100644
index 0000000000000000000000000000000000000000..aef81190f3867851ff60179a349d439b449513be
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8m.main+fp.dp.d
@@ -0,0 +1,63 @@ 
+#name: Valid armv8-m.main+fp.dp
+#as: -march=armv8-m.main+fp.dp
+#source: fpv5-d16.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-wince-*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe00 0b00 	vseleq.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe18 8b08 	vselvs.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe2f fb0f 	vselge.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe3a ab0a 	vselgt.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00 	vmaxnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe88 8b08 	vmaxnm.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe8f fb0f 	vmaxnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe8a ab0a 	vmaxnm.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40 	vminnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe88 8b48 	vminnm.f64	d8, d8, d8
+0[0-9a-f]+ <[^>]+> fe8f fb4f 	vminnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe8a ab4a 	vminnm.f64	d10, d10, d10
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> febc 0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0bc8 	vcvtn.s32.f64	s1, d8
+0[0-9a-f]+ <[^>]+> febe fb4f 	vcvtp.u32.f64	s30, d15
+0[0-9a-f]+ <[^>]+> feff fb4a 	vcvtm.u32.f64	s31, d10
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb7 1b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> eeb6 ab4a 	vrintr.f64	d10, d10
+0[0-9a-f]+ <[^>]+> feb8 0b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb9 1b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> feba ab4a 	vrintp.f64	d10, d10
+0[0-9a-f]+ <[^>]+> febb ab4a 	vrintm.f64	d10, d10
+0[0-9a-f]+ <[^>]+> eeb3 0bc0 	vcvtt.f16.f64	s0, d0
+0[0-9a-f]+ <[^>]+> eef3 0b48 	vcvtb.f16.f64	s1, d8
+0[0-9a-f]+ <[^>]+> eeb3 fbcf 	vcvtt.f16.f64	s30, d15
+0[0-9a-f]+ <[^>]+> eef3 fb4a 	vcvtb.f16.f64	s31, d10
+0[0-9a-f]+ <[^>]+> eeb2 0bc0 	vcvtt.f64.f16	d0, s0
+0[0-9a-f]+ <[^>]+> eeb2 8b60 	vcvtb.f64.f16	d8, s1
+0[0-9a-f]+ <[^>]+> eeb2 fbcf 	vcvtt.f64.f16	d15, s30
+0[0-9a-f]+ <[^>]+> eeb2 ab6f 	vcvtb.f64.f16	d10, s31
diff --git a/gas/testsuite/gas/arm/attr-ext-fpv5-d16.d b/gas/testsuite/gas/arm/attr-ext-fpv5-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..eb09cd2ea5e36e4b511c9d5193331e237fed2018
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-fpv5-d16.d
@@ -0,0 +1,14 @@ 
+# name: attributes for fpv5-d16 using architecture extensions
+# source: blank.s
+# as: -march=armv7e-m+fp.dp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7E-M"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
diff --git a/gas/testsuite/gas/arm/attr-ext-fpv5.d b/gas/testsuite/gas/arm/attr-ext-fpv5.d
new file mode 100644
index 0000000000000000000000000000000000000000..e671e32bcd45a392f86e438e07886187e2c321f2
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-fpv5.d
@@ -0,0 +1,15 @@ 
+# name: attributes for fpv5 using architecture extensions
+# source: blank.s
+# as: -march=armv7e-m+fpv5
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7E-M"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/attr-ext-idiv.d b/gas/testsuite/gas/arm/attr-ext-idiv.d
new file mode 100644
index 0000000000000000000000000000000000000000..2be50d55278d4f1eb3ca2151371a48c836ae7c52
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-idiv.d
@@ -0,0 +1,15 @@ 
+# name: attributes for idiv using architecture extensions
+# source: blank.s
+# as: -march=armv7-r+idiv
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-R"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/attr-ext-mp.d b/gas/testsuite/gas/arm/attr-ext-mp.d
new file mode 100644
index 0000000000000000000000000000000000000000..cc3972dc46de01338b6550d5a0a66db72b6bf222
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-mp.d
@@ -0,0 +1,15 @@ 
+# name: attributes for mp using architecture extensions
+# source: blank.s
+# as: -march=armv7-a+mp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
diff --git a/gas/testsuite/gas/arm/attr-ext-neon-fp16.d b/gas/testsuite/gas/arm/attr-ext-neon-fp16.d
new file mode 100644
index 0000000000000000000000000000000000000000..b35305ff2ae60489ebe5a7850bc312604a67d0b4
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-neon-fp16.d
@@ -0,0 +1,20 @@ 
+# name: attributes for neon-fp16 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+neon-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
+  Tag_FP_HP_extension: Allowed
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-ext-neon-vfpv3.d b/gas/testsuite/gas/arm/attr-ext-neon-vfpv3.d
new file mode 100644
index 0000000000000000000000000000000000000000..3a5017eb578211ff553467522487c096e078a747
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-neon-vfpv3.d
@@ -0,0 +1,16 @@ 
+# name: attributes for neon-vfpv3 using architecture extensions
+# source: blank.s
+# as: -march=armv7-a+simd
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
diff --git a/gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d b/gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d
new file mode 100644
index 0000000000000000000000000000000000000000..a41b079f5ec316afe022b4e599f2d4b36ae76946
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d
@@ -0,0 +1,19 @@ 
+# name: attributes for neon-vfpv4 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+simd
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-ext-sec.d b/gas/testsuite/gas/arm/attr-ext-sec.d
new file mode 100644
index 0000000000000000000000000000000000000000..0e48879a9af8321a659692d65fdd8a8aea425397
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-sec.d
@@ -0,0 +1,15 @@ 
+# name: attributes for sec using architecture extensions
+# source: blank.s
+# as: -march=armv7-a+sec
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d
new file mode 100644
index 0000000000000000000000000000000000000000..f7150b98e9a7b402365f4a6f895165da217e8afb
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d
@@ -0,0 +1,21 @@ 
+# name: attributes for architecture extension vfpv3-d16-fp16
+# source: blank.s
+# as: -march=armv7ve+vfpv3-d16-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_FP_HP_extension: Allowed
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
+
+
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..90799e6d80ddd277cab1f86ddfbc1e54da5d03d0
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d
@@ -0,0 +1,14 @@ 
+# name: attributes for architecture extension vfpv3-d16
+# source: blank.s
+# as: -march=armv7+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7"
+  Tag_CPU_arch: v7
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d b/gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d
new file mode 100644
index 0000000000000000000000000000000000000000..13412319ef5ed0fdf9e4a8d590a9226af4b1aab8
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d
@@ -0,0 +1,20 @@ 
+# name: attributes for architecture extension vfpv3-fp16
+# source: blank.s
+# as: -march=armv7ve+vfpv3-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_FP_HP_extension: Allowed
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
+
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3.d b/gas/testsuite/gas/arm/attr-ext-vfpv3.d
new file mode 100644
index 0000000000000000000000000000000000000000..7c7ed5388d6e7bd234d3e3263e366f6fa6a09658
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3.d
@@ -0,0 +1,15 @@ 
+# name: attributes for architecture extension vfpv3
+# source: blank.s
+# as: -march=armv7a+vfpv3
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7A"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d b/gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d
new file mode 100644
index 0000000000000000000000000000000000000000..bd510562e76fcbe4c5906eb1891d554de3c0c76e
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d
@@ -0,0 +1,17 @@ 
+# name: attributes for vfpv3xd-fp16 using architecture extensions
+# source: blank.s
+# as: -march=armv7-r+vfpv3xd-fp16
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-R"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_ABI_HardFP_use: SP only
+  Tag_FP_HP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv3xd.d b/gas/testsuite/gas/arm/attr-ext-vfpv3xd.d
new file mode 100644
index 0000000000000000000000000000000000000000..3ced8198abf6d5329587babb0b1053b17a16a83a
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv3xd.d
@@ -0,0 +1,16 @@ 
+# name: attributes for vfpv3xd using architecture extensions
+# source: blank.s
+# as: -march=armv7-r+fp.sp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7-R"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d b/gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..6e1a160384252954bf402397d71c9d98cae49878
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d
@@ -0,0 +1,18 @@ 
+# name: attributes for vfpv4-d16 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d b/gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d
new file mode 100644
index 0000000000000000000000000000000000000000..06bb494da299c893084233825c436e22eeb08852
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d
@@ -0,0 +1,15 @@ 
+# name: attributes for vfpv4-sp-d16 using architecture extensions
+# source: blank.s
+# as: -march=armv7e-m+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7E-M"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/attr-ext-vfpv4.d b/gas/testsuite/gas/arm/attr-ext-vfpv4.d
new file mode 100644
index 0000000000000000000000000000000000000000..397fba340594d763ffb06376ffd15f9032c79a29
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-ext-vfpv4.d
@@ -0,0 +1,18 @@ 
+# name: attributes for vfpv4 using architecture extensions
+# source: blank.s
+# as: -march=armv7ve+vfpv4
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "7VE"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d b/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d
index ab729454a0531f3eb4e7c9e95de85d2323740aa8..9a6369aef0ae8524f0a2885b8f24aaf0a1b13f95 100644
--- a/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d
+++ b/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d
@@ -1,14 +1,12 @@ 
 # name: attributes for -mfpu=neon-fp16
 # source: blank.s
-# as: -mfpu=neon-fp16
+# as: -march=armv7-a+neon-fp16
 # readelf: -A
 # This test is only valid on EABI based ports.
 # target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
+#...
   Tag_ARM_ISA_use: Yes
-  Tag_THUMB_ISA_use: Thumb-1
+  Tag_THUMB_ISA_use: Thumb-2
   Tag_FP_arch: VFPv3
   Tag_Advanced_SIMD_arch: NEONv1
   Tag_FP_HP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/dotprod-mandatory-ext.d b/gas/testsuite/gas/arm/dotprod-mandatory-ext.d
new file mode 100644
index 0000000000000000000000000000000000000000..34f6a69ab80e82967f18d7377d5a0604c38270ef
--- /dev/null
+++ b/gas/testsuite/gas/arm/dotprod-mandatory-ext.d
@@ -0,0 +1,297 @@ 
+#as: -march=armv8.4-a+simd
+#source: dotprod.s
+#objdump: -d
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+.* <.*>:
+.*:	fc220d10 	vudot.u8	d0, d2, d0
+.*:	fe220d10 	vudot.u8	d0, d2, d0\[0\]
+.*:	fc220d18 	vudot.u8	d0, d2, d8
+.*:	fe220d18 	vudot.u8	d0, d2, d8\[0\]
+.*:	fc220d1f 	vudot.u8	d0, d2, d15
+.*:	fe220d1f 	vudot.u8	d0, d2, d15\[0\]
+.*:	fc2f0d10 	vudot.u8	d0, d15, d0
+.*:	fe2f0d10 	vudot.u8	d0, d15, d0\[0\]
+.*:	fc2f0d18 	vudot.u8	d0, d15, d8
+.*:	fe2f0d18 	vudot.u8	d0, d15, d8\[0\]
+.*:	fc2f0d1f 	vudot.u8	d0, d15, d15
+.*:	fe2f0d1f 	vudot.u8	d0, d15, d15\[0\]
+.*:	fc2e0d90 	vudot.u8	d0, d30, d0
+.*:	fe2e0d90 	vudot.u8	d0, d30, d0\[0\]
+.*:	fc2e0d98 	vudot.u8	d0, d30, d8
+.*:	fe2e0d98 	vudot.u8	d0, d30, d8\[0\]
+.*:	fc2e0d9f 	vudot.u8	d0, d30, d15
+.*:	fe2e0d9f 	vudot.u8	d0, d30, d15\[0\]
+.*:	fc227d10 	vudot.u8	d7, d2, d0
+.*:	fe227d10 	vudot.u8	d7, d2, d0\[0\]
+.*:	fc227d18 	vudot.u8	d7, d2, d8
+.*:	fe227d18 	vudot.u8	d7, d2, d8\[0\]
+.*:	fc227d1f 	vudot.u8	d7, d2, d15
+.*:	fe227d1f 	vudot.u8	d7, d2, d15\[0\]
+.*:	fc2f7d10 	vudot.u8	d7, d15, d0
+.*:	fe2f7d10 	vudot.u8	d7, d15, d0\[0\]
+.*:	fc2f7d18 	vudot.u8	d7, d15, d8
+.*:	fe2f7d18 	vudot.u8	d7, d15, d8\[0\]
+.*:	fc2f7d1f 	vudot.u8	d7, d15, d15
+.*:	fe2f7d1f 	vudot.u8	d7, d15, d15\[0\]
+.*:	fc2e7d90 	vudot.u8	d7, d30, d0
+.*:	fe2e7d90 	vudot.u8	d7, d30, d0\[0\]
+.*:	fc2e7d98 	vudot.u8	d7, d30, d8
+.*:	fe2e7d98 	vudot.u8	d7, d30, d8\[0\]
+.*:	fc2e7d9f 	vudot.u8	d7, d30, d15
+.*:	fe2e7d9f 	vudot.u8	d7, d30, d15\[0\]
+.*:	fc620d10 	vudot.u8	d16, d2, d0
+.*:	fe620d10 	vudot.u8	d16, d2, d0\[0\]
+.*:	fc620d18 	vudot.u8	d16, d2, d8
+.*:	fe620d18 	vudot.u8	d16, d2, d8\[0\]
+.*:	fc620d1f 	vudot.u8	d16, d2, d15
+.*:	fe620d1f 	vudot.u8	d16, d2, d15\[0\]
+.*:	fc6f0d10 	vudot.u8	d16, d15, d0
+.*:	fe6f0d10 	vudot.u8	d16, d15, d0\[0\]
+.*:	fc6f0d18 	vudot.u8	d16, d15, d8
+.*:	fe6f0d18 	vudot.u8	d16, d15, d8\[0\]
+.*:	fc6f0d1f 	vudot.u8	d16, d15, d15
+.*:	fe6f0d1f 	vudot.u8	d16, d15, d15\[0\]
+.*:	fc6e0d90 	vudot.u8	d16, d30, d0
+.*:	fe6e0d90 	vudot.u8	d16, d30, d0\[0\]
+.*:	fc6e0d98 	vudot.u8	d16, d30, d8
+.*:	fe6e0d98 	vudot.u8	d16, d30, d8\[0\]
+.*:	fc6e0d9f 	vudot.u8	d16, d30, d15
+.*:	fe6e0d9f 	vudot.u8	d16, d30, d15\[0\]
+.*:	fc62fd10 	vudot.u8	d31, d2, d0
+.*:	fe62fd10 	vudot.u8	d31, d2, d0\[0\]
+.*:	fc62fd18 	vudot.u8	d31, d2, d8
+.*:	fe62fd18 	vudot.u8	d31, d2, d8\[0\]
+.*:	fc62fd1f 	vudot.u8	d31, d2, d15
+.*:	fe62fd1f 	vudot.u8	d31, d2, d15\[0\]
+.*:	fc6ffd10 	vudot.u8	d31, d15, d0
+.*:	fe6ffd10 	vudot.u8	d31, d15, d0\[0\]
+.*:	fc6ffd18 	vudot.u8	d31, d15, d8
+.*:	fe6ffd18 	vudot.u8	d31, d15, d8\[0\]
+.*:	fc6ffd1f 	vudot.u8	d31, d15, d15
+.*:	fe6ffd1f 	vudot.u8	d31, d15, d15\[0\]
+.*:	fc6efd90 	vudot.u8	d31, d30, d0
+.*:	fe6efd90 	vudot.u8	d31, d30, d0\[0\]
+.*:	fc6efd98 	vudot.u8	d31, d30, d8
+.*:	fe6efd98 	vudot.u8	d31, d30, d8\[0\]
+.*:	fc6efd9f 	vudot.u8	d31, d30, d15
+.*:	fe6efd9f 	vudot.u8	d31, d30, d15\[0\]
+.*:	fc220d00 	vsdot.s8	d0, d2, d0
+.*:	fe220d00 	vsdot.s8	d0, d2, d0\[0\]
+.*:	fc220d08 	vsdot.s8	d0, d2, d8
+.*:	fe220d08 	vsdot.s8	d0, d2, d8\[0\]
+.*:	fc220d0f 	vsdot.s8	d0, d2, d15
+.*:	fe220d0f 	vsdot.s8	d0, d2, d15\[0\]
+.*:	fc2f0d00 	vsdot.s8	d0, d15, d0
+.*:	fe2f0d00 	vsdot.s8	d0, d15, d0\[0\]
+.*:	fc2f0d08 	vsdot.s8	d0, d15, d8
+.*:	fe2f0d08 	vsdot.s8	d0, d15, d8\[0\]
+.*:	fc2f0d0f 	vsdot.s8	d0, d15, d15
+.*:	fe2f0d0f 	vsdot.s8	d0, d15, d15\[0\]
+.*:	fc2e0d80 	vsdot.s8	d0, d30, d0
+.*:	fe2e0d80 	vsdot.s8	d0, d30, d0\[0\]
+.*:	fc2e0d88 	vsdot.s8	d0, d30, d8
+.*:	fe2e0d88 	vsdot.s8	d0, d30, d8\[0\]
+.*:	fc2e0d8f 	vsdot.s8	d0, d30, d15
+.*:	fe2e0d8f 	vsdot.s8	d0, d30, d15\[0\]
+.*:	fc227d00 	vsdot.s8	d7, d2, d0
+.*:	fe227d00 	vsdot.s8	d7, d2, d0\[0\]
+.*:	fc227d08 	vsdot.s8	d7, d2, d8
+.*:	fe227d08 	vsdot.s8	d7, d2, d8\[0\]
+.*:	fc227d0f 	vsdot.s8	d7, d2, d15
+.*:	fe227d0f 	vsdot.s8	d7, d2, d15\[0\]
+.*:	fc2f7d00 	vsdot.s8	d7, d15, d0
+.*:	fe2f7d00 	vsdot.s8	d7, d15, d0\[0\]
+.*:	fc2f7d08 	vsdot.s8	d7, d15, d8
+.*:	fe2f7d08 	vsdot.s8	d7, d15, d8\[0\]
+.*:	fc2f7d0f 	vsdot.s8	d7, d15, d15
+.*:	fe2f7d0f 	vsdot.s8	d7, d15, d15\[0\]
+.*:	fc2e7d80 	vsdot.s8	d7, d30, d0
+.*:	fe2e7d80 	vsdot.s8	d7, d30, d0\[0\]
+.*:	fc2e7d88 	vsdot.s8	d7, d30, d8
+.*:	fe2e7d88 	vsdot.s8	d7, d30, d8\[0\]
+.*:	fc2e7d8f 	vsdot.s8	d7, d30, d15
+.*:	fe2e7d8f 	vsdot.s8	d7, d30, d15\[0\]
+.*:	fc620d00 	vsdot.s8	d16, d2, d0
+.*:	fe620d00 	vsdot.s8	d16, d2, d0\[0\]
+.*:	fc620d08 	vsdot.s8	d16, d2, d8
+.*:	fe620d08 	vsdot.s8	d16, d2, d8\[0\]
+.*:	fc620d0f 	vsdot.s8	d16, d2, d15
+.*:	fe620d0f 	vsdot.s8	d16, d2, d15\[0\]
+.*:	fc6f0d00 	vsdot.s8	d16, d15, d0
+.*:	fe6f0d00 	vsdot.s8	d16, d15, d0\[0\]
+.*:	fc6f0d08 	vsdot.s8	d16, d15, d8
+.*:	fe6f0d08 	vsdot.s8	d16, d15, d8\[0\]
+.*:	fc6f0d0f 	vsdot.s8	d16, d15, d15
+.*:	fe6f0d0f 	vsdot.s8	d16, d15, d15\[0\]
+.*:	fc6e0d80 	vsdot.s8	d16, d30, d0
+.*:	fe6e0d80 	vsdot.s8	d16, d30, d0\[0\]
+.*:	fc6e0d88 	vsdot.s8	d16, d30, d8
+.*:	fe6e0d88 	vsdot.s8	d16, d30, d8\[0\]
+.*:	fc6e0d8f 	vsdot.s8	d16, d30, d15
+.*:	fe6e0d8f 	vsdot.s8	d16, d30, d15\[0\]
+.*:	fc62fd00 	vsdot.s8	d31, d2, d0
+.*:	fe62fd00 	vsdot.s8	d31, d2, d0\[0\]
+.*:	fc62fd08 	vsdot.s8	d31, d2, d8
+.*:	fe62fd08 	vsdot.s8	d31, d2, d8\[0\]
+.*:	fc62fd0f 	vsdot.s8	d31, d2, d15
+.*:	fe62fd0f 	vsdot.s8	d31, d2, d15\[0\]
+.*:	fc6ffd00 	vsdot.s8	d31, d15, d0
+.*:	fe6ffd00 	vsdot.s8	d31, d15, d0\[0\]
+.*:	fc6ffd08 	vsdot.s8	d31, d15, d8
+.*:	fe6ffd08 	vsdot.s8	d31, d15, d8\[0\]
+.*:	fc6ffd0f 	vsdot.s8	d31, d15, d15
+.*:	fe6ffd0f 	vsdot.s8	d31, d15, d15\[0\]
+.*:	fc6efd80 	vsdot.s8	d31, d30, d0
+.*:	fe6efd80 	vsdot.s8	d31, d30, d0\[0\]
+.*:	fc6efd88 	vsdot.s8	d31, d30, d8
+.*:	fe6efd88 	vsdot.s8	d31, d30, d8\[0\]
+.*:	fc6efd8f 	vsdot.s8	d31, d30, d15
+.*:	fe6efd8f 	vsdot.s8	d31, d30, d15\[0\]
+.*:	fc240d50 	vudot.u8	q0, q2, q0
+.*:	fe240d70 	vudot.u8	q0, q2, d0\[1\]
+.*:	fc240d5e 	vudot.u8	q0, q2, q7
+.*:	fe240d77 	vudot.u8	q0, q2, d7\[1\]
+.*:	fc240d7e 	vudot.u8	q0, q2, q15
+.*:	fe240d7f 	vudot.u8	q0, q2, d15\[1\]
+.*:	fc260d50 	vudot.u8	q0, q3, q0
+.*:	fe260d70 	vudot.u8	q0, q3, d0\[1\]
+.*:	fc260d5e 	vudot.u8	q0, q3, q7
+.*:	fe260d77 	vudot.u8	q0, q3, d7\[1\]
+.*:	fc260d7e 	vudot.u8	q0, q3, q15
+.*:	fe260d7f 	vudot.u8	q0, q3, d15\[1\]
+.*:	fc2c0dd0 	vudot.u8	q0, q14, q0
+.*:	fe2c0df0 	vudot.u8	q0, q14, d0\[1\]
+.*:	fc2c0dde 	vudot.u8	q0, q14, q7
+.*:	fe2c0df7 	vudot.u8	q0, q14, d7\[1\]
+.*:	fc2c0dfe 	vudot.u8	q0, q14, q15
+.*:	fe2c0dff 	vudot.u8	q0, q14, d15\[1\]
+.*:	fc242d50 	vudot.u8	q1, q2, q0
+.*:	fe242d70 	vudot.u8	q1, q2, d0\[1\]
+.*:	fc242d5e 	vudot.u8	q1, q2, q7
+.*:	fe242d77 	vudot.u8	q1, q2, d7\[1\]
+.*:	fc242d7e 	vudot.u8	q1, q2, q15
+.*:	fe242d7f 	vudot.u8	q1, q2, d15\[1\]
+.*:	fc262d50 	vudot.u8	q1, q3, q0
+.*:	fe262d70 	vudot.u8	q1, q3, d0\[1\]
+.*:	fc262d5e 	vudot.u8	q1, q3, q7
+.*:	fe262d77 	vudot.u8	q1, q3, d7\[1\]
+.*:	fc262d7e 	vudot.u8	q1, q3, q15
+.*:	fe262d7f 	vudot.u8	q1, q3, d15\[1\]
+.*:	fc2c2dd0 	vudot.u8	q1, q14, q0
+.*:	fe2c2df0 	vudot.u8	q1, q14, d0\[1\]
+.*:	fc2c2dde 	vudot.u8	q1, q14, q7
+.*:	fe2c2df7 	vudot.u8	q1, q14, d7\[1\]
+.*:	fc2c2dfe 	vudot.u8	q1, q14, q15
+.*:	fe2c2dff 	vudot.u8	q1, q14, d15\[1\]
+.*:	fc24cd50 	vudot.u8	q6, q2, q0
+.*:	fe24cd70 	vudot.u8	q6, q2, d0\[1\]
+.*:	fc24cd5e 	vudot.u8	q6, q2, q7
+.*:	fe24cd77 	vudot.u8	q6, q2, d7\[1\]
+.*:	fc24cd7e 	vudot.u8	q6, q2, q15
+.*:	fe24cd7f 	vudot.u8	q6, q2, d15\[1\]
+.*:	fc26cd50 	vudot.u8	q6, q3, q0
+.*:	fe26cd70 	vudot.u8	q6, q3, d0\[1\]
+.*:	fc26cd5e 	vudot.u8	q6, q3, q7
+.*:	fe26cd77 	vudot.u8	q6, q3, d7\[1\]
+.*:	fc26cd7e 	vudot.u8	q6, q3, q15
+.*:	fe26cd7f 	vudot.u8	q6, q3, d15\[1\]
+.*:	fc2ccdd0 	vudot.u8	q6, q14, q0
+.*:	fe2ccdf0 	vudot.u8	q6, q14, d0\[1\]
+.*:	fc2ccdde 	vudot.u8	q6, q14, q7
+.*:	fe2ccdf7 	vudot.u8	q6, q14, d7\[1\]
+.*:	fc2ccdfe 	vudot.u8	q6, q14, q15
+.*:	fe2ccdff 	vudot.u8	q6, q14, d15\[1\]
+.*:	fc64ad50 	vudot.u8	q13, q2, q0
+.*:	fe64ad70 	vudot.u8	q13, q2, d0\[1\]
+.*:	fc64ad5e 	vudot.u8	q13, q2, q7
+.*:	fe64ad77 	vudot.u8	q13, q2, d7\[1\]
+.*:	fc64ad7e 	vudot.u8	q13, q2, q15
+.*:	fe64ad7f 	vudot.u8	q13, q2, d15\[1\]
+.*:	fc66ad50 	vudot.u8	q13, q3, q0
+.*:	fe66ad70 	vudot.u8	q13, q3, d0\[1\]
+.*:	fc66ad5e 	vudot.u8	q13, q3, q7
+.*:	fe66ad77 	vudot.u8	q13, q3, d7\[1\]
+.*:	fc66ad7e 	vudot.u8	q13, q3, q15
+.*:	fe66ad7f 	vudot.u8	q13, q3, d15\[1\]
+.*:	fc6cadd0 	vudot.u8	q13, q14, q0
+.*:	fe6cadf0 	vudot.u8	q13, q14, d0\[1\]
+.*:	fc6cadde 	vudot.u8	q13, q14, q7
+.*:	fe6cadf7 	vudot.u8	q13, q14, d7\[1\]
+.*:	fc6cadfe 	vudot.u8	q13, q14, q15
+.*:	fe6cadff 	vudot.u8	q13, q14, d15\[1\]
+.*:	fc240d40 	vsdot.s8	q0, q2, q0
+.*:	fe240d60 	vsdot.s8	q0, q2, d0\[1\]
+.*:	fc240d4e 	vsdot.s8	q0, q2, q7
+.*:	fe240d67 	vsdot.s8	q0, q2, d7\[1\]
+.*:	fc240d6e 	vsdot.s8	q0, q2, q15
+.*:	fe240d6f 	vsdot.s8	q0, q2, d15\[1\]
+.*:	fc260d40 	vsdot.s8	q0, q3, q0
+.*:	fe260d60 	vsdot.s8	q0, q3, d0\[1\]
+.*:	fc260d4e 	vsdot.s8	q0, q3, q7
+.*:	fe260d67 	vsdot.s8	q0, q3, d7\[1\]
+.*:	fc260d6e 	vsdot.s8	q0, q3, q15
+.*:	fe260d6f 	vsdot.s8	q0, q3, d15\[1\]
+.*:	fc2c0dc0 	vsdot.s8	q0, q14, q0
+.*:	fe2c0de0 	vsdot.s8	q0, q14, d0\[1\]
+.*:	fc2c0dce 	vsdot.s8	q0, q14, q7
+.*:	fe2c0de7 	vsdot.s8	q0, q14, d7\[1\]
+.*:	fc2c0dee 	vsdot.s8	q0, q14, q15
+.*:	fe2c0def 	vsdot.s8	q0, q14, d15\[1\]
+.*:	fc242d40 	vsdot.s8	q1, q2, q0
+.*:	fe242d60 	vsdot.s8	q1, q2, d0\[1\]
+.*:	fc242d4e 	vsdot.s8	q1, q2, q7
+.*:	fe242d67 	vsdot.s8	q1, q2, d7\[1\]
+.*:	fc242d6e 	vsdot.s8	q1, q2, q15
+.*:	fe242d6f 	vsdot.s8	q1, q2, d15\[1\]
+.*:	fc262d40 	vsdot.s8	q1, q3, q0
+.*:	fe262d60 	vsdot.s8	q1, q3, d0\[1\]
+.*:	fc262d4e 	vsdot.s8	q1, q3, q7
+.*:	fe262d67 	vsdot.s8	q1, q3, d7\[1\]
+.*:	fc262d6e 	vsdot.s8	q1, q3, q15
+.*:	fe262d6f 	vsdot.s8	q1, q3, d15\[1\]
+.*:	fc2c2dc0 	vsdot.s8	q1, q14, q0
+.*:	fe2c2de0 	vsdot.s8	q1, q14, d0\[1\]
+.*:	fc2c2dce 	vsdot.s8	q1, q14, q7
+.*:	fe2c2de7 	vsdot.s8	q1, q14, d7\[1\]
+.*:	fc2c2dee 	vsdot.s8	q1, q14, q15
+.*:	fe2c2def 	vsdot.s8	q1, q14, d15\[1\]
+.*:	fc24cd40 	vsdot.s8	q6, q2, q0
+.*:	fe24cd60 	vsdot.s8	q6, q2, d0\[1\]
+.*:	fc24cd4e 	vsdot.s8	q6, q2, q7
+.*:	fe24cd67 	vsdot.s8	q6, q2, d7\[1\]
+.*:	fc24cd6e 	vsdot.s8	q6, q2, q15
+.*:	fe24cd6f 	vsdot.s8	q6, q2, d15\[1\]
+.*:	fc26cd40 	vsdot.s8	q6, q3, q0
+.*:	fe26cd60 	vsdot.s8	q6, q3, d0\[1\]
+.*:	fc26cd4e 	vsdot.s8	q6, q3, q7
+.*:	fe26cd67 	vsdot.s8	q6, q3, d7\[1\]
+.*:	fc26cd6e 	vsdot.s8	q6, q3, q15
+.*:	fe26cd6f 	vsdot.s8	q6, q3, d15\[1\]
+.*:	fc2ccdc0 	vsdot.s8	q6, q14, q0
+.*:	fe2ccde0 	vsdot.s8	q6, q14, d0\[1\]
+.*:	fc2ccdce 	vsdot.s8	q6, q14, q7
+.*:	fe2ccde7 	vsdot.s8	q6, q14, d7\[1\]
+.*:	fc2ccdee 	vsdot.s8	q6, q14, q15
+.*:	fe2ccdef 	vsdot.s8	q6, q14, d15\[1\]
+.*:	fc64ad40 	vsdot.s8	q13, q2, q0
+.*:	fe64ad60 	vsdot.s8	q13, q2, d0\[1\]
+.*:	fc64ad4e 	vsdot.s8	q13, q2, q7
+.*:	fe64ad67 	vsdot.s8	q13, q2, d7\[1\]
+.*:	fc64ad6e 	vsdot.s8	q13, q2, q15
+.*:	fe64ad6f 	vsdot.s8	q13, q2, d15\[1\]
+.*:	fc66ad40 	vsdot.s8	q13, q3, q0
+.*:	fe66ad60 	vsdot.s8	q13, q3, d0\[1\]
+.*:	fc66ad4e 	vsdot.s8	q13, q3, q7
+.*:	fe66ad67 	vsdot.s8	q13, q3, d7\[1\]
+.*:	fc66ad6e 	vsdot.s8	q13, q3, q15
+.*:	fe66ad6f 	vsdot.s8	q13, q3, d15\[1\]
+.*:	fc6cadc0 	vsdot.s8	q13, q14, q0
+.*:	fe6cade0 	vsdot.s8	q13, q14, d0\[1\]
+.*:	fc6cadce 	vsdot.s8	q13, q14, q7
+.*:	fe6cade7 	vsdot.s8	q13, q14, d7\[1\]
+.*:	fc6cadee 	vsdot.s8	q13, q14, q15
+.*:	fe6cadef 	vsdot.s8	q13, q14, d15\[1\]
diff --git a/gas/testsuite/gas/arm/fpv5-d16.s b/gas/testsuite/gas/arm/fpv5-d16.s
new file mode 100644
index 0000000000000000000000000000000000000000..9d9d4d68560f8653a272853f4c0a5b3a3ac51aa1
--- /dev/null
+++ b/gas/testsuite/gas/arm/fpv5-d16.s
@@ -0,0 +1,58 @@ 
+	.syntax unified
+	.text
+
+	.thumb
+	vseleq.f32	s0, s0, s0
+	vselvs.f32	s1, s1, s1
+	vselge.f32	s30, s30, s30
+	vselgt.f32	s31, s31, s31
+	vseleq.f64	d0, d0, d0
+	vselvs.f64	d8, d8, d8
+	vselge.f64	d15, d15, d15
+	vselgt.f64	d10, d10, d10
+	vmaxnm.f32	s0, s0, s0
+	vmaxnm.f32	s1, s1, s1
+	vmaxnm.f32	s30, s30, s30
+	vmaxnm.f32	s31, s31, s31
+	vmaxnm.f64	d0, d0, d0
+	vmaxnm.f64	d8, d8, d8
+	vmaxnm.f64	d15, d15, d15
+	vmaxnm.f64	d10, d10, d10
+	vminnm.f32	s0, s0, s0
+	vminnm.f32	s1, s1, s1
+	vminnm.f32	s30, s30, s30
+	vminnm.f32	s31, s31, s31
+	vminnm.f64	d0, d0, d0
+	vminnm.f64	d8, d8, d8
+	vminnm.f64	d15, d15, d15
+	vminnm.f64	d10, d10, d10
+	vcvta.s32.f32	s0, s0
+	vcvtn.s32.f32	s1, s1
+	vcvtp.u32.f32	s30, s30
+	vcvtm.u32.f32	s31, s31
+	vcvta.s32.f64	s0, d0
+	vcvtn.s32.f64	s1, d8
+	vcvtp.u32.f64	s30, d15
+	vcvtm.u32.f64	s31, d10
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
+	vrintz.f64	d0, d0
+        vrintx.f64	d1, d1
+        vrintr.f64	d10, d10
+	vrinta.f64	d0, d0
+	vrintn.f64	d1, d1
+	vrintp.f64	d10, d10
+	vrintm.f64	d10, d10
+	vcvtt.f16.f64	s0, d0
+	vcvtb.f16.f64	s1, d8
+	vcvtt.f16.f64	s30, d15
+	vcvtb.f16.f64	s31, d10
+	vcvtt.f64.f16	d0, s0
+	vcvtb.f64.f16	d8, s1
+	vcvtt.f64.f16	d15, s30
+	vcvtb.f64.f16	d10, s31
diff --git a/gas/testsuite/gas/arm/fpv5-sp-d16.s b/gas/testsuite/gas/arm/fpv5-sp-d16.s
new file mode 100644
index 0000000000000000000000000000000000000000..1d9e2439f0cc06bceb46b2de1e67eb1f65d95fe3
--- /dev/null
+++ b/gas/testsuite/gas/arm/fpv5-sp-d16.s
@@ -0,0 +1,27 @@ 
+	.syntax unified
+	.text
+
+	.thumb
+	vseleq.f32	s0, s0, s0
+	vselvs.f32	s1, s1, s1
+	vselge.f32	s30, s30, s30
+	vselgt.f32	s31, s31, s31
+	vmaxnm.f32	s0, s0, s0
+	vmaxnm.f32	s1, s1, s1
+	vmaxnm.f32	s30, s30, s30
+	vmaxnm.f32	s31, s31, s31
+	vminnm.f32	s0, s0, s0
+	vminnm.f32	s1, s1, s1
+	vminnm.f32	s30, s30, s30
+	vminnm.f32	s31, s31, s31
+	vcvta.s32.f32	s0, s0
+	vcvtn.s32.f32	s1, s1
+	vcvtp.u32.f32	s30, s30
+	vcvtm.u32.f32	s31, s31
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 5888330250494670d5b0e79f552589d309d3c1ac..4f5c89f8383b419832fea1aca0335553cbe4221d 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -205,6 +205,7 @@ 
 					     | FPU_VFP_EXT_ARMV8xD)
 #define FPU_NEON_ARMV8	  (FPU_NEON_EXT_V1   | FPU_NEON_EXT_FMA	   \
 					     | FPU_NEON_EXT_ARMV8)
+#define FPU_NEON_ARMV8_1  (FPU_NEON_ARMV8    | FPU_NEON_EXT_RDMA)
 #define FPU_CRYPTO_ARMV8  (FPU_CRYPTO_EXT_ARMV8)
 #define FPU_VFP_HARD	  (FPU_VFP_EXT_V1xD  | FPU_VFP_EXT_V1	   \
 					     | FPU_VFP_EXT_V2	   \
@@ -264,19 +265,35 @@ 
 						    | FPU_NEON_EXT_DOTPROD)
 #define ARCH_CRC_ARMV8		ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
 #define FPU_ARCH_NEON_VFP_ARMV8_1					 \
-				ARM_FEATURE_COPROC (FPU_NEON_ARMV8	 \
-						    | FPU_VFP_ARMV8	 \
-						    | FPU_NEON_EXT_RDMA)
+				ARM_FEATURE_COPROC (FPU_NEON_ARMV8_1	 \
+						    | FPU_VFP_ARMV8)
 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1				 \
 				ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8	 \
-						    | FPU_NEON_ARMV8	 \
-						    | FPU_VFP_ARMV8	 \
-						    | FPU_NEON_EXT_RDMA)
+						    | FPU_NEON_ARMV8_1	 \
+						    | FPU_VFP_ARMV8)
+
 #define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8					 \
 				ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD \
-						    | FPU_NEON_ARMV8	 \
+						    | FPU_NEON_ARMV8_1	 \
 						    | FPU_VFP_ARMV8)
 
+#define FPU_ARCH_NEON_VFP_ARMV8_2_FP16					 \
+      ARM_FEATURE (0, ARM_EXT2_FP16_INST,				 \
+		   FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8)
+
+#define FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML				 \
+      ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML,		 \
+		   FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8)
+
+#define FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML				 \
+      ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML,		 \
+		   FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 | FPU_NEON_EXT_DOTPROD)
+
+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4				 \
+			      ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8	 \
+						  | FPU_NEON_ARMV8_1	 \
+						  | FPU_VFP_ARMV8	 \
+						  | FPU_NEON_EXT_DOTPROD)
 
 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)