[17/42] i386: Emulate MMX mmx_pextrw with SSE

Message ID 20190215135812.32306-18-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V6: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 15, 2019, 1:57 p.m.
Emulate MMX mmx_pextrw with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
 gcc/config/i386/mmx.md | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

-- 
2.20.1

Comments

H.J. Lu Feb. 15, 2019, 4 p.m. | #1
On Fri, Feb 15, 2019 at 6:03 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> Emulate MMX mmx_pextrw with SSE.  Only SSE register source operand is

> allowed.

>

>         PR target/89021

>         * config/i386/mmx.md (mmx_pextrw): Add SSE emulation.

> ---

>  gcc/config/i386/mmx.md | 16 +++++++++-------

>  1 file changed, 9 insertions(+), 7 deletions(-)

>

> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> index 3ea64e9aabe..678eaa713dc 100644

> --- a/gcc/config/i386/mmx.md

> +++ b/gcc/config/i386/mmx.md

> @@ -1310,16 +1310,18 @@

>     (set_attr "mode" "DI")])

>

>  (define_insn "mmx_pextrw"

> -  [(set (match_operand:SI 0 "register_operand" "=r")

> +  [(set (match_operand:SI 0 "register_operand" "=r,r")

>          (zero_extend:SI

>           (vec_select:HI

> -           (match_operand:V4HI 1 "register_operand" "y")

> -           (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]

> -  "TARGET_SSE || TARGET_3DNOW_A"

> -  "pextrw\t{%2, %1, %0|%0, %1, %2}"

> -  [(set_attr "type" "mmxcvt")

> +           (match_operand:V4HI 1 "register_operand" "y,Yv")

> +           (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE)

> +   && (TARGET_SSE || TARGET_3DNOW_A)"

> +  "%vpextrw\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64")

> +   (set_attr "type" "mmxcvt,sselog1")

>     (set_attr "length_immediate" "1")

> -   (set_attr "mode" "DI")])

> +   (set_attr "mode" "DI,TI")])

>

>  (define_expand "mmx_pshufw"

>    [(match_operand:V4HI 0 "register_operand")

> --

> 2.20.1

>


Here is the updated patch for mmx_pextrw.  It should be

(define_insn "mmx_pextrw"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (zero_extend:SI
          (vec_select:HI
            (match_operand:V4HI 1 "register_operand" "y,Yv")
            (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]
  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
   && (TARGET_SSE || TARGET_3DNOW_A)"
  "@
   pextrw\t{%2, %1, %0|%0, %1, %2}
   %vpextrw\t{%2, %1, %0|%0, %1, %2}"
  [(set_attr "mmx_isa" "native,x64")
   (set_attr "type" "mmxcvt,sselog1")
   (set_attr "length_immediate" "1")
   (set_attr "mode" "DI,TI")])


-- 
H.J.
From 17bd9eb652aff70a72680f444fbb169344cf563b Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Fri, 25 Jan 2019 11:27:35 -0800
Subject: [PATCH 17/42] i386: Emulate MMX mmx_pextrw with SSE

Emulate MMX mmx_pextrw with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
 gcc/config/i386/mmx.md | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 3ea64e9aabe..1818957f670 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1310,16 +1310,20 @@
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_pextrw"
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
         (zero_extend:SI
 	  (vec_select:HI
-	    (match_operand:V4HI 1 "register_operand" "y")
-	    (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
-  "TARGET_SSE || TARGET_3DNOW_A"
-  "pextrw\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "mmxcvt")
+	    (match_operand:V4HI 1 "register_operand" "y,Yv")
+	    (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && (TARGET_SSE || TARGET_3DNOW_A)"
+  "@
+   pextrw\t{%2, %1, %0|%0, %1, %2}
+   %vpextrw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64")
+   (set_attr "type" "mmxcvt,sselog1")
    (set_attr "length_immediate" "1")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI")])
 
 (define_expand "mmx_pshufw"
   [(match_operand:V4HI 0 "register_operand")

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 3ea64e9aabe..678eaa713dc 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1310,16 +1310,18 @@ 
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_pextrw"
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
         (zero_extend:SI
 	  (vec_select:HI
-	    (match_operand:V4HI 1 "register_operand" "y")
-	    (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
-  "TARGET_SSE || TARGET_3DNOW_A"
-  "pextrw\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "mmxcvt")
+	    (match_operand:V4HI 1 "register_operand" "y,Yv")
+	    (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && (TARGET_SSE || TARGET_3DNOW_A)"
+  "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64")
+   (set_attr "type" "mmxcvt,sselog1")
    (set_attr "length_immediate" "1")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI")])
 
 (define_expand "mmx_pshufw"
   [(match_operand:V4HI 0 "register_operand")