[41/40] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE

Message ID CAFULd4bo1A90nvaBtOtSWw-Qc=azp1Jqz9Jj6bTL1extutpcVg@mail.gmail.com
State New
Headers show
Series
  • V5: Emulate MMX intrinsics with SSE
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Commit Message

Uros Bizjak Feb. 14, 2019, 6:17 p.m.
You will also need the following (untested) patch that prevents
allocation of MMX registers with TARGET_MMX_WITH_SSE in several insn
patterns.

2019-02-14  UroŇ° Bizjak  <ubizjak@gmail.com>

    PR target/89021
    * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
    * config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto.
    (*vec_concatv2sf_sse): Ditto.
    (*vec_concatv2si_sse4_1): Ditto.
    (*vec_concatv2si): Ditto.
    (*vec_concatv4si_0): Ditto.
    (*vec_concatv2di_0): Ditto.

Uros.

Patch

Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md	(revision 268854)
+++ config/i386/i386.md	(working copy)
@@ -3855,6 +3855,10 @@ 
 	      (const_string "avx512bw")
 	   ]
 	   (const_string "*")))
+   (set (attr "mmx_isa")
+     (if_then_else (eq_attr "alternative" "5,6")
+		   (const_string "native")
+		   (const_string "*")))
    (set (attr "type")
      (cond [(eq_attr "alternative" "0,1,2,4")
 	      (const_string "multi")
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md	(revision 268855)
+++ config/i386/sse.md	(working copy)
@@ -7241,6 +7241,10 @@ 
 	      (const_string "mmxmov")
 	   ]
 	   (const_string "sselog")))
+   (set (attr "mmx_isa")
+     (if_then_else (eq_attr "alternative" "7,8")
+		   (const_string "native")
+		   (const_string "*")))
    (set (attr "prefix_data16")
      (if_then_else (eq_attr "alternative" "3,4")
 		   (const_string "1")
@@ -7276,7 +7280,8 @@ 
    movss\t{%1, %0|%0, %1}
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
-  [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
+  [(set_attr "mmx_isa" "*,*,native,native")
+   (set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
    (set_attr "mode" "V4SF,SF,DI,DI")])
 
 (define_insn "*vec_concatv4sf"
@@ -14549,6 +14554,10 @@ 
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "isa" "noavx,noavx,avx,avx512dq,noavx,noavx,avx,*,*,*")
+   (set (attr "mmx_isa")
+     (if_then_else (eq_attr "alternative" "8,9")
+		   (const_string "native")
+		   (const_string "*")))
    (set (attr "type")
      (cond [(eq_attr "alternative" "7")
 	      (const_string "ssemov")
@@ -14586,6 +14595,7 @@ 
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "isa" "sse2,sse2,*,*,*,*")
+   (set_attr "mmx_isa" "*,*,*,*,native,native")
    (set_attr "type" "sselog,ssemov,sselog,ssemov,mmxcvt,mmxmov")
    (set_attr "mode" "TI,TI,V4SF,SF,DI,DI")])
 
@@ -14615,7 +14625,8 @@ 
   "@
    %vmovq\t{%1, %0|%0, %1}
    movq2dq\t{%1, %0|%0, %1}"
-  [(set_attr "type" "ssemov")
+  [(set_attr "mmx_isa" "*,native")
+   (set_attr "type" "ssemov")
    (set_attr "prefix" "maybe_vex,orig")
    (set_attr "mode" "TI")])
 
@@ -14690,6 +14701,7 @@ 
    %vmovq\t{%1, %0|%0, %1}
    movq2dq\t{%1, %0|%0, %1}"
   [(set_attr "isa" "x64,*,*")
+   (set_attr "mmx_isa" "*,*,native")
    (set_attr "type" "ssemov")
    (set_attr "prefix_rex" "1,*,*")
    (set_attr "prefix" "maybe_vex,maybe_vex,orig")