[37/40] i386: Allow MMX intrinsic emulation with SSE

Message ID 20190214123031.13301-38-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V5: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 14, 2019, 12:30 p.m.
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.

For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.

gcc/

	PR target/89021
	* config/i386/i386-builtin.def: Enable MMX intrinsics with
	SSE/SSE2/SSSE3.
	* config/i386/i386.c (ix86_option_override_internal): Don't
	enable MMX ISA with TARGET_MMX_WITH_SSE by default.
	(ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
	SSE/SSE2/SSSE3.
	(ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
	intrinsics with TARGET_MMX_WITH_SSE.
	* config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

gcc/testsuite/

	PR target/89021
	* gcc.target/i386/pr82483-1.c: Error only on ia32.
	* gcc.target/i386/pr82483-2.c: Likewise.
---
 gcc/config/i386/i386-builtin.def          | 126 +++++++++++-----------
 gcc/config/i386/i386.c                    |  46 ++++++--
 gcc/config/i386/mmintrin.h                |  10 +-
 gcc/testsuite/gcc.target/i386/pr82483-1.c |   2 +-
 gcc/testsuite/gcc.target/i386/pr82483-2.c |   2 +-
 5 files changed, 110 insertions(+), 76 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 14, 2019, 8:06 p.m. | #1
On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA

> by default with TARGET_MMX_WITH_SSE.

>

> For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit

> mode since MMX intrinsics can be emulated wit SSE.

>

> gcc/

>

>         PR target/89021

>         * config/i386/i386-builtin.def: Enable MMX intrinsics with

>         SSE/SSE2/SSSE3.

>         * config/i386/i386.c (ix86_option_override_internal): Don't

>         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

>         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

>         SSE/SSE2/SSSE3.

>         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

>         intrinsics with TARGET_MMX_WITH_SSE.

>         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

>

> gcc/testsuite/

>

>         PR target/89021

>         * gcc.target/i386/pr82483-1.c: Error only on ia32.

>         * gcc.target/i386/pr82483-2.c: Likewise.

> ---

>  gcc/config/i386/i386-builtin.def          | 126 +++++++++++-----------

>  gcc/config/i386/i386.c                    |  46 ++++++--

>  gcc/config/i386/mmintrin.h                |  10 +-

>  gcc/testsuite/gcc.target/i386/pr82483-1.c |   2 +-

>  gcc/testsuite/gcc.target/i386/pr82483-2.c |   2 +-

>  5 files changed, 110 insertions(+), 76 deletions(-)

>

> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def

> index 88005f4687f..10a9d631f29 100644

> --- a/gcc/config/i386/i386-builtin.def

> +++ b/gcc/config/i386/i386-builtin.def

> @@ -100,7 +100,7 @@ BDESC (0, 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKN

>  BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID)

>

>  /* MMX */

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)

>

>  /* 3DNow! */

>  BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID)

> @@ -442,68 +442,68 @@ BDESC (0, 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNO

>  BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)

>

>  /* MMX */

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

>

>  /* 3DNow! */

>  BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)

> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> index a9abbe8706b..1d417e08734 100644

> --- a/gcc/config/i386/i386.c

> +++ b/gcc/config/i386/i386.c

> @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

>        opts->x_target_flags

>         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

>

> -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> -        explicitly disable any of these.  In particular, disabling SSE and

> -        MMX for kernel code is extremely useful.  */

> +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> +        explicitly disable any of these.  In particular, disabling SSE

> +        and MMX for kernel code is extremely useful.  */

>        if (!ix86_arch_specified)

>        opts->x_ix86_isa_flags

> -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> +               ? 0 : OPTION_MASK_ISA_MMX)

>              | TARGET_SUBTARGET64_ISA_DEFAULT)

>              & ~opts->x_ix86_isa_flags_explicit);


Please split the above into two clauses, the first that sets SSE and
MMX by default, and the second to or with

opts->x_ix86_isa_flags
     |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit


> @@ -4216,8 +4219,10 @@ ix86_option_override_internal (bool main_args_p,

>    if (!TARGET_80387_P (opts->x_target_flags))

>      opts->x_target_flags |= MASK_NO_FANCY_MATH_387;

>

> -  /* Turn on MMX builtins for -msse.  */

> -  if (TARGET_SSE_P (opts->x_ix86_isa_flags))

> +  /* Turn on MMX builtins for -msse.  Don't enable MMX ISA with

> +     TARGET_MMX_WITH_SSE.  */

> +  if (TARGET_SSE_P (opts->x_ix86_isa_flags)

> +      && !TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

>      opts->x_ix86_isa_flags

>        |= OPTION_MASK_ISA_MMX & ~opts->x_ix86_isa_flags_explicit;

>

> @@ -31769,14 +31774,17 @@ ix86_init_mmx_sse_builtins (void)

>                VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);

>

>    /* MMX access to the vec_init patterns.  */

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v2si",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_init_v2si",

>                      V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);

>

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v4hi",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_init_v4hi",

>                      V4HI_FTYPE_HI_HI_HI_HI,

>                      IX86_BUILTIN_VEC_INIT_V4HI);

>

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v8qi",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_init_v8qi",

>                      V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,

>                      IX86_BUILTIN_VEC_INIT_V8QI);

>

> @@ -31798,7 +31806,8 @@ ix86_init_mmx_sse_builtins (void)

>                      "__builtin_ia32_vec_ext_v4hi",

>                      HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);

>

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_ext_v2si",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_ext_v2si",

>                      SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);

>

>    def_builtin_const (OPTION_MASK_ISA_SSE2, 0, "__builtin_ia32_vec_ext_v16qi",

> @@ -36931,6 +36940,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,

>         == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))

>        && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)

>      isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);

> +  /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when

> +     MMX is disabled.  */

> +  if (TARGET_MMX_WITH_SSE)

> +    {

> +      if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))

> +          == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))

> +         && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0)

> +       isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX);

> +      if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))

> +          == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))

> +         && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0)

> +       isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX);

> +      if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))

> +          == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))

> +         && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0)

> +       isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX);

> +    }

>    if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)

>      {

>        char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,

> diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h

> index 238b3df3121..7b613658111 100644

> --- a/gcc/config/i386/mmintrin.h

> +++ b/gcc/config/i386/mmintrin.h

> @@ -30,7 +30,7 @@

>  #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__

>  #pragma GCC push_options

>  #ifdef __x86_64__

> -#pragma GCC target("sse,mmx")

> +#pragma GCC target("sse2")


You will need to involve __MMX_WITH_SSE__ here, probably to something like:

#ifdef __MMX_WITH_SSE__
#pragma GCC target("sse2")
#elif defined __x86_64__
#pragma GCC target("sse,mmx")
#else
#pragma GCC target("mmx")
#endif

>  #else

>  #pragma GCC target("mmx")

>  #endif

> @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)

>  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

>  #ifndef __SSE2__

>  #pragma GCC push_options

> +#ifdef __x86_64__


#ifdef __MMX_WITH_SSE__

> +#pragma GCC target("sse2")

> +#else

>  #pragma GCC target("sse2,mmx")

> +#endif

>  #define __DISABLE_SSE2__

>  #endif /* __SSE2__ */

>

> @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)

>  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

>  #ifndef __SSE2__

>  #pragma GCC push_options

> +#ifdef __x86_64__


#ifdef __MMX_WITH_SSE__

> +#pragma GCC target("sse2")

> +#else

>  #pragma GCC target("sse2,mmx")

> +#endif

>  #define __DISABLE_SSE2__

>  #endif /* __SSE2__ */

>

> diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c b/gcc/testsuite/gcc.target/i386/pr82483-1.c

> index 59a59dc8dfe..b2028d8dc5e 100644

> --- a/gcc/testsuite/gcc.target/i386/pr82483-1.c

> +++ b/gcc/testsuite/gcc.target/i386/pr82483-1.c

> @@ -1,7 +1,7 @@

>  /* PR target/82483 */

>  /* { dg-do compile } */

>  /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */

> -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */

> +/* { dg-error "needs isa option" "" { target ia32 } 0 } */

>

>  #include <x86intrin.h>

>

> diff --git a/gcc/testsuite/gcc.target/i386/pr82483-2.c b/gcc/testsuite/gcc.target/i386/pr82483-2.c

> index 305ddbd6c64..c92de405cb3 100644

> --- a/gcc/testsuite/gcc.target/i386/pr82483-2.c

> +++ b/gcc/testsuite/gcc.target/i386/pr82483-2.c

> @@ -1,7 +1,7 @@

>  /* PR target/82483 */

>  /* { dg-do compile } */

>  /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */

> -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */

> +/* { dg-error "needs isa option" "" { target ia32 } 0 } */

>

>  #include <x86intrin.h>

>

> --

> 2.20.1

>
H.J. Lu Feb. 14, 2019, 8:50 p.m. | #2
On Thu, Feb 14, 2019 at 12:07 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >

> > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA

> > by default with TARGET_MMX_WITH_SSE.

> >

> > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit

> > mode since MMX intrinsics can be emulated wit SSE.

> >

> > gcc/

> >

> >         PR target/89021

> >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> >         SSE/SSE2/SSSE3.

> >         * config/i386/i386.c (ix86_option_override_internal): Don't

> >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> >         SSE/SSE2/SSSE3.

> >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> >         intrinsics with TARGET_MMX_WITH_SSE.

> >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> >


>

> > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > index a9abbe8706b..1d417e08734 100644

> > --- a/gcc/config/i386/i386.c

> > +++ b/gcc/config/i386/i386.c

> > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> >        opts->x_target_flags

> >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> >

> > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > -        explicitly disable any of these.  In particular, disabling SSE and

> > -        MMX for kernel code is extremely useful.  */

> > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > +        explicitly disable any of these.  In particular, disabling SSE

> > +        and MMX for kernel code is extremely useful.  */

> >        if (!ix86_arch_specified)

> >        opts->x_ix86_isa_flags

> > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > +               ? 0 : OPTION_MASK_ISA_MMX)

> >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> >              & ~opts->x_ix86_isa_flags_explicit);

>

> Please split the above into two clauses, the first that sets SSE and

> MMX by default, and the second to or with

>

> opts->x_ix86_isa_flags

>      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

>


Like this?

      /* Enable the SSE and MMX builtins by default.  Don't enable MMX
         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to
         explicitly disable any of these.  In particular, disabling SSE
         and MMX for kernel code is extremely useful.  */
      if (!ix86_arch_specified)
        {
          opts->x_ix86_isa_flags
            |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
                 | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
                    ? 0 : OPTION_MASK_ISA_MMX))
                & ~opts->x_ix86_isa_flags_explicit);
          opts->x_ix86_isa_flags
            |= (TARGET_SUBTARGET64_ISA_DEFAULT
                & ~opts->x_ix86_isa_flags_explicit);
        }


> > diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h

> > index 238b3df3121..7b613658111 100644

> > --- a/gcc/config/i386/mmintrin.h

> > +++ b/gcc/config/i386/mmintrin.h

> > @@ -30,7 +30,7 @@

> >  #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__

> >  #pragma GCC push_options

> >  #ifdef __x86_64__

> > -#pragma GCC target("sse,mmx")

> > +#pragma GCC target("sse2")

>

> You will need to involve __MMX_WITH_SSE__ here, probably to something like:

>

> #ifdef __MMX_WITH_SSE__

> #pragma GCC target("sse2")

> #elif defined __x86_64__

> #pragma GCC target("sse,mmx")

> #else

> #pragma GCC target("mmx")

> #endif

>

> >  #else

> >  #pragma GCC target("mmx")

> >  #endif

> > @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)

> >  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

> >  #ifndef __SSE2__

> >  #pragma GCC push_options

> > +#ifdef __x86_64__

>

> #ifdef __MMX_WITH_SSE__

>

> > +#pragma GCC target("sse2")

> > +#else

> >  #pragma GCC target("sse2,mmx")

> > +#endif

> >  #define __DISABLE_SSE2__

> >  #endif /* __SSE2__ */

> >

> > @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)

> >  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

> >  #ifndef __SSE2__

> >  #pragma GCC push_options

> > +#ifdef __x86_64__

>

> #ifdef __MMX_WITH_SSE__

>

> > +#pragma GCC target("sse2")

> > +#else

> >  #pragma GCC target("sse2,mmx")

> > +#endif

> >  #define __DISABLE_SSE2__

> >  #endif /* __SSE2__ */

> >

> > diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c b/gcc/testsuite/gcc.target/i386/pr82483-1.c


I will do

diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
index 238b3df3121..c4b2e0c7b25 100644
--- a/gcc/config/i386/mmintrin.h
+++ b/gcc/config/i386/mmintrin.h
@@ -29,7 +29,9 @@

 #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
 #pragma GCC push_options
-#ifdef __x86_64__
+#ifdef __MMX_WITH_SSE__
+#pragma GCC target("sse2")
+#elif defined __x86_64__
 #pragma GCC target("sse,mmx")
 #else
 #pragma GCC target("mmx")
@@ -315,7 +317,11 @@ _m_paddd (__m64 __m1, __m64 __m2)
 /* Add the 64-bit values in M1 to the 64-bit values in M2.  */
 #ifndef __SSE2__
 #pragma GCC push_options
+#ifdef __MMX_WITH_SSE__
+#pragma GCC target("sse2")
+#else
 #pragma GCC target("sse2,mmx")
+#endif
 #define __DISABLE_SSE2__
 #endif /* __SSE2__ */

@@ -427,7 +433,11 @@ _m_psubd (__m64 __m1, __m64 __m2)
 /* Add the 64-bit values in M1 to the 64-bit values in M2.  */
 #ifndef __SSE2__
 #pragma GCC push_options
+#ifdef __MMX_WITH_SSE__
+#pragma GCC target("sse2")
+#else
 #pragma GCC target("sse2,mmx")
+#endif
 #define __DISABLE_SSE2__
 #endif

Thanks.

-- 
H.J.
Uros Bizjak Feb. 14, 2019, 8:54 p.m. | #3
On Thu, Feb 14, 2019 at 9:50 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> On Thu, Feb 14, 2019 at 12:07 PM Uros Bizjak <ubizjak@gmail.com> wrote:

> >

> > On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> > >

> > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA

> > > by default with TARGET_MMX_WITH_SSE.

> > >

> > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit

> > > mode since MMX intrinsics can be emulated wit SSE.

> > >

> > > gcc/

> > >

> > >         PR target/89021

> > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > >         SSE/SSE2/SSSE3.

> > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > >         SSE/SSE2/SSSE3.

> > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > >         intrinsics with TARGET_MMX_WITH_SSE.

> > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > >

>

> >

> > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > index a9abbe8706b..1d417e08734 100644

> > > --- a/gcc/config/i386/i386.c

> > > +++ b/gcc/config/i386/i386.c

> > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > >        opts->x_target_flags

> > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > >

> > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > -        MMX for kernel code is extremely useful.  */

> > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > +        explicitly disable any of these.  In particular, disabling SSE

> > > +        and MMX for kernel code is extremely useful.  */

> > >        if (!ix86_arch_specified)

> > >        opts->x_ix86_isa_flags

> > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > >              & ~opts->x_ix86_isa_flags_explicit);

> >

> > Please split the above into two clauses, the first that sets SSE and

> > MMX by default, and the second to or with

> >

> > opts->x_ix86_isa_flags

> >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> >

>

> Like this?


Yes, but also split the comment.

Thanks,
Uros.

>       /* Enable the SSE and MMX builtins by default.  Don't enable MMX

>          ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

>          explicitly disable any of these.  In particular, disabling SSE

>          and MMX for kernel code is extremely useful.  */

>       if (!ix86_arch_specified)

>         {

>           opts->x_ix86_isa_flags

>             |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

>                  | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

>                     ? 0 : OPTION_MASK_ISA_MMX))

>                 & ~opts->x_ix86_isa_flags_explicit);

>           opts->x_ix86_isa_flags

>             |= (TARGET_SUBTARGET64_ISA_DEFAULT

>                 & ~opts->x_ix86_isa_flags_explicit);

>         }

>

>

> > > diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h

> > > index 238b3df3121..7b613658111 100644

> > > --- a/gcc/config/i386/mmintrin.h

> > > +++ b/gcc/config/i386/mmintrin.h

> > > @@ -30,7 +30,7 @@

> > >  #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__

> > >  #pragma GCC push_options

> > >  #ifdef __x86_64__

> > > -#pragma GCC target("sse,mmx")

> > > +#pragma GCC target("sse2")

> >

> > You will need to involve __MMX_WITH_SSE__ here, probably to something like:

> >

> > #ifdef __MMX_WITH_SSE__

> > #pragma GCC target("sse2")

> > #elif defined __x86_64__

> > #pragma GCC target("sse,mmx")

> > #else

> > #pragma GCC target("mmx")

> > #endif

> >

> > >  #else

> > >  #pragma GCC target("mmx")

> > >  #endif

> > > @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)

> > >  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

> > >  #ifndef __SSE2__

> > >  #pragma GCC push_options

> > > +#ifdef __x86_64__

> >

> > #ifdef __MMX_WITH_SSE__

> >

> > > +#pragma GCC target("sse2")

> > > +#else

> > >  #pragma GCC target("sse2,mmx")

> > > +#endif

> > >  #define __DISABLE_SSE2__

> > >  #endif /* __SSE2__ */

> > >

> > > @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)

> > >  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

> > >  #ifndef __SSE2__

> > >  #pragma GCC push_options

> > > +#ifdef __x86_64__

> >

> > #ifdef __MMX_WITH_SSE__

> >

> > > +#pragma GCC target("sse2")

> > > +#else

> > >  #pragma GCC target("sse2,mmx")

> > > +#endif

> > >  #define __DISABLE_SSE2__

> > >  #endif /* __SSE2__ */

> > >

> > > diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c b/gcc/testsuite/gcc.target/i386/pr82483-1.c

>

> I will do

>

> diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h

> index 238b3df3121..c4b2e0c7b25 100644

> --- a/gcc/config/i386/mmintrin.h

> +++ b/gcc/config/i386/mmintrin.h

> @@ -29,7 +29,9 @@

>

>  #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__

>  #pragma GCC push_options

> -#ifdef __x86_64__

> +#ifdef __MMX_WITH_SSE__

> +#pragma GCC target("sse2")

> +#elif defined __x86_64__

>  #pragma GCC target("sse,mmx")

>  #else

>  #pragma GCC target("mmx")

> @@ -315,7 +317,11 @@ _m_paddd (__m64 __m1, __m64 __m2)

>  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

>  #ifndef __SSE2__

>  #pragma GCC push_options

> +#ifdef __MMX_WITH_SSE__

> +#pragma GCC target("sse2")

> +#else

>  #pragma GCC target("sse2,mmx")

> +#endif

>  #define __DISABLE_SSE2__

>  #endif /* __SSE2__ */

>

> @@ -427,7 +433,11 @@ _m_psubd (__m64 __m1, __m64 __m2)

>  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

>  #ifndef __SSE2__

>  #pragma GCC push_options

> +#ifdef __MMX_WITH_SSE__

> +#pragma GCC target("sse2")

> +#else

>  #pragma GCC target("sse2,mmx")

> +#endif

>  #define __DISABLE_SSE2__

>  #endif

>

> Thanks.

>

> --

> H.J.
H.J. Lu Feb. 14, 2019, 9:02 p.m. | #4
On Thu, Feb 14, 2019 at 12:54 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> On Thu, Feb 14, 2019 at 9:50 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >

> > On Thu, Feb 14, 2019 at 12:07 PM Uros Bizjak <ubizjak@gmail.com> wrote:

> > >

> > > On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> > > >

> > > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA

> > > > by default with TARGET_MMX_WITH_SSE.

> > > >

> > > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit

> > > > mode since MMX intrinsics can be emulated wit SSE.

> > > >

> > > > gcc/

> > > >

> > > >         PR target/89021

> > > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > > >         SSE/SSE2/SSSE3.

> > > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > > >         SSE/SSE2/SSSE3.

> > > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > > >         intrinsics with TARGET_MMX_WITH_SSE.

> > > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > > >

> >

> > >

> > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > > index a9abbe8706b..1d417e08734 100644

> > > > --- a/gcc/config/i386/i386.c

> > > > +++ b/gcc/config/i386/i386.c

> > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > > >        opts->x_target_flags

> > > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > > >

> > > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > > -        MMX for kernel code is extremely useful.  */

> > > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > > +        explicitly disable any of these.  In particular, disabling SSE

> > > > +        and MMX for kernel code is extremely useful.  */

> > > >        if (!ix86_arch_specified)

> > > >        opts->x_ix86_isa_flags

> > > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > > >              & ~opts->x_ix86_isa_flags_explicit);

> > >

> > > Please split the above into two clauses, the first that sets SSE and

> > > MMX by default, and the second to or with

> > >

> > > opts->x_ix86_isa_flags

> > >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> > >

> >

> > Like this?

>

> Yes, but also split the comment.


I will go with

     /* Enable by default the SSE and MMX builtins.  Do allow the user to
         explicitly disable any of these.  In particular, disabling SSE and
         MMX for kernel code is extremely useful.  */
      if (!ix86_arch_specified)
        {
          /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */
          opts->x_ix86_isa_flags
            |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
                 | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
                    ? 0 : OPTION_MASK_ISA_MMX))
                & ~opts->x_ix86_isa_flags_explicit);
          opts->x_ix86_isa_flags
            |= (TARGET_SUBTARGET64_ISA_DEFAULT
                & ~opts->x_ix86_isa_flags_explicit);
        }


-- 
H.J.
Uros Bizjak Feb. 14, 2019, 10:57 p.m. | #5
On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> > > > > gcc/

> > > > >

> > > > >         PR target/89021

> > > > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > > > >         SSE/SSE2/SSSE3.

> > > > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > > > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > > > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > > > >         SSE/SSE2/SSSE3.

> > > > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > > > >         intrinsics with TARGET_MMX_WITH_SSE.

> > > > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > > > >

> > >

> > > >

> > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > > > index a9abbe8706b..1d417e08734 100644

> > > > > --- a/gcc/config/i386/i386.c

> > > > > +++ b/gcc/config/i386/i386.c

> > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > > > >        opts->x_target_flags

> > > > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > > > >

> > > > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > > > -        MMX for kernel code is extremely useful.  */

> > > > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > > > +        explicitly disable any of these.  In particular, disabling SSE

> > > > > +        and MMX for kernel code is extremely useful.  */

> > > > >        if (!ix86_arch_specified)

> > > > >        opts->x_ix86_isa_flags

> > > > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > > > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > > > >              & ~opts->x_ix86_isa_flags_explicit);

> > > >

> > > > Please split the above into two clauses, the first that sets SSE and

> > > > MMX by default, and the second to or with

> > > >

> > > > opts->x_ix86_isa_flags

> > > >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> > > >

> > >

> > > Like this?

> >

> > Yes, but also split the comment.

>

> I will go with

>

>      /* Enable by default the SSE and MMX builtins.  Do allow the user to

>          explicitly disable any of these.  In particular, disabling SSE and

>          MMX for kernel code is extremely useful.  */

>       if (!ix86_arch_specified)

>         {

>           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

>           opts->x_ix86_isa_flags

>             |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

>                  | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

>                     ? 0 : OPTION_MASK_ISA_MMX))

>                 & ~opts->x_ix86_isa_flags_explicit);

>           opts->x_ix86_isa_flags

>             |= (TARGET_SUBTARGET64_ISA_DEFAULT

>                 & ~opts->x_ix86_isa_flags_explicit);

>         }


I'll commit the following patch that finally defines
TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX
bit from x_i86_isa_flags, like:

      if (!ix86_arch_specified)
    opts->x_ix86_isa_flags
      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;

      /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */
      if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
    opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

Uros.
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 268907)
+++ config/i386/i386.c	(working copy)
@@ -4165,14 +4165,9 @@ ix86_option_override_internal (bool main_args_p,
       opts->x_target_flags
 	|= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
 
-      /* Enable by default the SSE and MMX builtins.  Do allow the user to
-	 explicitly disable any of these.  In particular, disabling SSE and
-	 MMX for kernel code is extremely useful.  */
       if (!ix86_arch_specified)
-      opts->x_ix86_isa_flags
-	|= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
-	     | TARGET_SUBTARGET64_ISA_DEFAULT)
-            & ~opts->x_ix86_isa_flags_explicit);
+	opts->x_ix86_isa_flags
+	  |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;
 
       if (TARGET_RTD_P (opts->x_target_flags))
 	warning (0,
Index: config/i386/i386.h
===================================================================
--- config/i386/i386.h	(revision 268907)
+++ config/i386/i386.h	(working copy)
@@ -633,7 +633,9 @@ extern tree x86_mfence;
 
 /* Extra bits to force on w/ 64-bit mode.  */
 #define TARGET_SUBTARGET64_DEFAULT 0
-#define TARGET_SUBTARGET64_ISA_DEFAULT 0
+/* Enable MMX, SSE and SSE2 by default.  */
+#define TARGET_SUBTARGET64_ISA_DEFAULT \
+  (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
 
 /* Replace MACH-O, ifdefs by in-line tests, where possible. 
    (a) Macros defined in config/i386/darwin.h  */
H.J. Lu Feb. 14, 2019, 11:12 p.m. | #6
On Thu, Feb 14, 2019 at 2:57 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu <hjl.tools@gmail.com> wrote:

>

> > > > > > gcc/

> > > > > >

> > > > > >         PR target/89021

> > > > > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > > > > >         SSE/SSE2/SSSE3.

> > > > > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > > > > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > > > > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > > > > >         SSE/SSE2/SSSE3.

> > > > > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > > > > >         intrinsics with TARGET_MMX_WITH_SSE.

> > > > > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > > > > >

> > > >

> > > > >

> > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > > > > index a9abbe8706b..1d417e08734 100644

> > > > > > --- a/gcc/config/i386/i386.c

> > > > > > +++ b/gcc/config/i386/i386.c

> > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > > > > >        opts->x_target_flags

> > > > > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > > > > >

> > > > > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > > > > -        MMX for kernel code is extremely useful.  */

> > > > > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > > > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > > > > +        explicitly disable any of these.  In particular, disabling SSE

> > > > > > +        and MMX for kernel code is extremely useful.  */

> > > > > >        if (!ix86_arch_specified)

> > > > > >        opts->x_ix86_isa_flags

> > > > > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > > > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > > > > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > > > > >              & ~opts->x_ix86_isa_flags_explicit);

> > > > >

> > > > > Please split the above into two clauses, the first that sets SSE and

> > > > > MMX by default, and the second to or with

> > > > >

> > > > > opts->x_ix86_isa_flags

> > > > >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> > > > >

> > > >

> > > > Like this?

> > >

> > > Yes, but also split the comment.

> >

> > I will go with

> >

> >      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> >          explicitly disable any of these.  In particular, disabling SSE and

> >          MMX for kernel code is extremely useful.  */

> >       if (!ix86_arch_specified)

> >         {

> >           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> >           opts->x_ix86_isa_flags

> >             |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> >                  | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> >                     ? 0 : OPTION_MASK_ISA_MMX))

> >                 & ~opts->x_ix86_isa_flags_explicit);

> >           opts->x_ix86_isa_flags

> >             |= (TARGET_SUBTARGET64_ISA_DEFAULT

> >                 & ~opts->x_ix86_isa_flags_explicit);

> >         }

>

> I'll commit the following patch that finally defines

> TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX

> bit from x_i86_isa_flags, like:

>

>       if (!ix86_arch_specified)

>     opts->x_ix86_isa_flags

>       |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;

>

>       /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

>       if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

>     opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;


I think it should be:

          /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */
          if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)
              && TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
            opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

Thanks.

-- 
H.J.
H.J. Lu Feb. 14, 2019, 11:14 p.m. | #7
On Thu, Feb 14, 2019 at 3:12 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> On Thu, Feb 14, 2019 at 2:57 PM Uros Bizjak <ubizjak@gmail.com> wrote:

> >

> > On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >

> > > > > > > gcc/

> > > > > > >

> > > > > > >         PR target/89021

> > > > > > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > > > > > >         SSE/SSE2/SSSE3.

> > > > > > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > > > > > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > > > > > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > > > > > >         SSE/SSE2/SSSE3.

> > > > > > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > > > > > >         intrinsics with TARGET_MMX_WITH_SSE.

> > > > > > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > > > > > >

> > > > >

> > > > > >

> > > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > > > > > index a9abbe8706b..1d417e08734 100644

> > > > > > > --- a/gcc/config/i386/i386.c

> > > > > > > +++ b/gcc/config/i386/i386.c

> > > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > > > > > >        opts->x_target_flags

> > > > > > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > > > > > >

> > > > > > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > > > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > > > > > -        MMX for kernel code is extremely useful.  */

> > > > > > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > > > > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > > > > > +        explicitly disable any of these.  In particular, disabling SSE

> > > > > > > +        and MMX for kernel code is extremely useful.  */

> > > > > > >        if (!ix86_arch_specified)

> > > > > > >        opts->x_ix86_isa_flags

> > > > > > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > > > > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > > > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > > > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > > > > > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > > > > > >              & ~opts->x_ix86_isa_flags_explicit);

> > > > > >

> > > > > > Please split the above into two clauses, the first that sets SSE and

> > > > > > MMX by default, and the second to or with

> > > > > >

> > > > > > opts->x_ix86_isa_flags

> > > > > >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> > > > > >

> > > > >

> > > > > Like this?

> > > >

> > > > Yes, but also split the comment.

> > >

> > > I will go with

> > >

> > >      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > >          explicitly disable any of these.  In particular, disabling SSE and

> > >          MMX for kernel code is extremely useful.  */

> > >       if (!ix86_arch_specified)

> > >         {

> > >           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> > >           opts->x_ix86_isa_flags

> > >             |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > >                  | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > >                     ? 0 : OPTION_MASK_ISA_MMX))

> > >                 & ~opts->x_ix86_isa_flags_explicit);

> > >           opts->x_ix86_isa_flags

> > >             |= (TARGET_SUBTARGET64_ISA_DEFAULT

> > >                 & ~opts->x_ix86_isa_flags_explicit);

> > >         }

> >

> > I'll commit the following patch that finally defines

> > TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX

> > bit from x_i86_isa_flags, like:

> >

> >       if (!ix86_arch_specified)

> >     opts->x_ix86_isa_flags

> >       |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;

> >

> >       /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> >       if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

> >     opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

>

> I think it should be:

>

>           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

>           if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)

                I meant opts->x_ix86_isa_flags_explicit.
>               && TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

>             opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

>

> Thanks.

>

> --

> H.J.




-- 
H.J.
Uros Bizjak Feb. 14, 2019, 11:21 p.m. | #8
On Fri, Feb 15, 2019 at 12:14 AM H.J. Lu <hjl.tools@gmail.com> wrote:

> > > > > > > > gcc/

> > > > > > > >

> > > > > > > >         PR target/89021

> > > > > > > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > > > > > > >         SSE/SSE2/SSSE3.

> > > > > > > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > > > > > > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > > > > > > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > > > > > > >         SSE/SSE2/SSSE3.

> > > > > > > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > > > > > > >         intrinsics with TARGET_MMX_WITH_SSE.

> > > > > > > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > > > > > > >

> > > > > >

> > > > > > >

> > > > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > > > > > > index a9abbe8706b..1d417e08734 100644

> > > > > > > > --- a/gcc/config/i386/i386.c

> > > > > > > > +++ b/gcc/config/i386/i386.c

> > > > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > > > > > > >        opts->x_target_flags

> > > > > > > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > > > > > > >

> > > > > > > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > > > > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > > > > > > -        MMX for kernel code is extremely useful.  */

> > > > > > > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > > > > > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > > > > > > +        explicitly disable any of these.  In particular, disabling SSE

> > > > > > > > +        and MMX for kernel code is extremely useful.  */

> > > > > > > >        if (!ix86_arch_specified)

> > > > > > > >        opts->x_ix86_isa_flags

> > > > > > > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > > > > > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > > > > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > > > > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > > > > > > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > > > > > > >              & ~opts->x_ix86_isa_flags_explicit);

> > > > > > >

> > > > > > > Please split the above into two clauses, the first that sets SSE and

> > > > > > > MMX by default, and the second to or with

> > > > > > >

> > > > > > > opts->x_ix86_isa_flags

> > > > > > >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> > > > > > >

> > > > > >

> > > > > > Like this?

> > > > >

> > > > > Yes, but also split the comment.

> > > >

> > > > I will go with

> > > >

> > > >      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > >          explicitly disable any of these.  In particular, disabling SSE and

> > > >          MMX for kernel code is extremely useful.  */

> > > >       if (!ix86_arch_specified)

> > > >         {

> > > >           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> > > >           opts->x_ix86_isa_flags

> > > >             |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > >                  | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > >                     ? 0 : OPTION_MASK_ISA_MMX))

> > > >                 & ~opts->x_ix86_isa_flags_explicit);

> > > >           opts->x_ix86_isa_flags

> > > >             |= (TARGET_SUBTARGET64_ISA_DEFAULT

> > > >                 & ~opts->x_ix86_isa_flags_explicit);

> > > >         }

> > >

> > > I'll commit the following patch that finally defines

> > > TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX

> > > bit from x_i86_isa_flags, like:

> > >

> > >       if (!ix86_arch_specified)

> > >     opts->x_ix86_isa_flags

> > >       |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;

> > >

> > >       /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> > >       if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

> > >     opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

> >

> > I think it should be:

> >

> >           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> >           if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)

>                 I meant opts->x_ix86_isa_flags_explicit.

> >               && TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

> >             opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;


Well ... I didn't test this part. OTOH, maybe this part is not needed,
MMX disabling can go *after*

  /* Turn on MMX builtins for -msse.  */
  if (TARGET_SSE_P (opts->x_ix86_isa_flags))
    opts->x_ix86_isa_flags
      |= OPTION_MASK_ISA_MMX & ~opts->x_ix86_isa_flags_explicit;

Uros.
H.J. Lu Feb. 14, 2019, 11:24 p.m. | #9
On Thu, Feb 14, 2019 at 3:21 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> On Fri, Feb 15, 2019 at 12:14 AM H.J. Lu <hjl.tools@gmail.com> wrote:

>

> > > > > > > > > gcc/

> > > > > > > > >

> > > > > > > > >         PR target/89021

> > > > > > > > >         * config/i386/i386-builtin.def: Enable MMX intrinsics with

> > > > > > > > >         SSE/SSE2/SSSE3.

> > > > > > > > >         * config/i386/i386.c (ix86_option_override_internal): Don't

> > > > > > > > >         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

> > > > > > > > >         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

> > > > > > > > >         SSE/SSE2/SSSE3.

> > > > > > > > >         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

> > > > > > > > >         intrinsics with TARGET_MMX_WITH_SSE.

> > > > > > > > >         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

> > > > > > > > >

> > > > > > >

> > > > > > > >

> > > > > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> > > > > > > > > index a9abbe8706b..1d417e08734 100644

> > > > > > > > > --- a/gcc/config/i386/i386.c

> > > > > > > > > +++ b/gcc/config/i386/i386.c

> > > > > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

> > > > > > > > >        opts->x_target_flags

> > > > > > > > >         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

> > > > > > > > >

> > > > > > > > > -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > > > > > > -        explicitly disable any of these.  In particular, disabling SSE and

> > > > > > > > > -        MMX for kernel code is extremely useful.  */

> > > > > > > > > +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> > > > > > > > > +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> > > > > > > > > +        explicitly disable any of these.  In particular, disabling SSE

> > > > > > > > > +        and MMX for kernel code is extremely useful.  */

> > > > > > > > >        if (!ix86_arch_specified)

> > > > > > > > >        opts->x_ix86_isa_flags

> > > > > > > > > -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> > > > > > > > > +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > > > > > > +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > > > > > > +               ? 0 : OPTION_MASK_ISA_MMX)

> > > > > > > > >              | TARGET_SUBTARGET64_ISA_DEFAULT)

> > > > > > > > >              & ~opts->x_ix86_isa_flags_explicit);

> > > > > > > >

> > > > > > > > Please split the above into two clauses, the first that sets SSE and

> > > > > > > > MMX by default, and the second to or with

> > > > > > > >

> > > > > > > > opts->x_ix86_isa_flags

> > > > > > > >      |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit

> > > > > > > >

> > > > > > >

> > > > > > > Like this?

> > > > > >

> > > > > > Yes, but also split the comment.

> > > > >

> > > > > I will go with

> > > > >

> > > > >      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> > > > >          explicitly disable any of these.  In particular, disabling SSE and

> > > > >          MMX for kernel code is extremely useful.  */

> > > > >       if (!ix86_arch_specified)

> > > > >         {

> > > > >           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> > > > >           opts->x_ix86_isa_flags

> > > > >             |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> > > > >                  | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> > > > >                     ? 0 : OPTION_MASK_ISA_MMX))

> > > > >                 & ~opts->x_ix86_isa_flags_explicit);

> > > > >           opts->x_ix86_isa_flags

> > > > >             |= (TARGET_SUBTARGET64_ISA_DEFAULT

> > > > >                 & ~opts->x_ix86_isa_flags_explicit);

> > > > >         }

> > > >

> > > > I'll commit the following patch that finally defines

> > > > TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX

> > > > bit from x_i86_isa_flags, like:

> > > >

> > > >       if (!ix86_arch_specified)

> > > >     opts->x_ix86_isa_flags

> > > >       |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;

> > > >

> > > >       /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> > > >       if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

> > > >     opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

> > >

> > > I think it should be:

> > >

> > >           /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE.  */

> > >           if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)

> >                 I meant opts->x_ix86_isa_flags_explicit.

> > >               && TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

> > >             opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;

>

> Well ... I didn't test this part. OTOH, maybe this part is not needed,

> MMX disabling can go *after*

>

>   /* Turn on MMX builtins for -msse.  */

>   if (TARGET_SSE_P (opts->x_ix86_isa_flags))

>     opts->x_ix86_isa_flags

>       |= OPTION_MASK_ISA_MMX & ~opts->x_ix86_isa_flags_explicit;

>


It works only if TARGET_SUBTARGET64_ISA_DEFAULT doesn't
include OPTION_MASK_ISA_MMX.

-- 
H.J.
Uros Bizjak Feb. 15, 2019, 12:04 p.m. | #10
On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA

> by default with TARGET_MMX_WITH_SSE.

>

> For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit

> mode since MMX intrinsics can be emulated wit SSE.

>

> gcc/

>

>         PR target/89021

>         * config/i386/i386-builtin.def: Enable MMX intrinsics with

>         SSE/SSE2/SSSE3.

>         * config/i386/i386.c (ix86_option_override_internal): Don't

>         enable MMX ISA with TARGET_MMX_WITH_SSE by default.

>         (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with

>         SSE/SSE2/SSSE3.

>         (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX

>         intrinsics with TARGET_MMX_WITH_SSE.

>         * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.

>

> gcc/testsuite/

>

>         PR target/89021

>         * gcc.target/i386/pr82483-1.c: Error only on ia32.

>         * gcc.target/i386/pr82483-2.c: Likewise.

> ---

>  gcc/config/i386/i386-builtin.def          | 126 +++++++++++-----------

>  gcc/config/i386/i386.c                    |  46 ++++++--

>  gcc/config/i386/mmintrin.h                |  10 +-

>  gcc/testsuite/gcc.target/i386/pr82483-1.c |   2 +-

>  gcc/testsuite/gcc.target/i386/pr82483-2.c |   2 +-

>  5 files changed, 110 insertions(+), 76 deletions(-)

>

> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def

> index 88005f4687f..10a9d631f29 100644

> --- a/gcc/config/i386/i386-builtin.def

> +++ b/gcc/config/i386/i386-builtin.def

> @@ -100,7 +100,7 @@ BDESC (0, 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKN

>  BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID)

>

>  /* MMX */

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)

>

>  /* 3DNow! */

>  BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID)

> @@ -442,68 +442,68 @@ BDESC (0, 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNO

>  BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)

>

>  /* MMX */

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> -

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)

> +

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)

> +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)

>

>  /* 3DNow! */

>  BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)

> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> index a9abbe8706b..1d417e08734 100644

> --- a/gcc/config/i386/i386.c

> +++ b/gcc/config/i386/i386.c

> @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,

>        opts->x_target_flags

>         |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;

>

> -      /* Enable by default the SSE and MMX builtins.  Do allow the user to

> -        explicitly disable any of these.  In particular, disabling SSE and

> -        MMX for kernel code is extremely useful.  */

> +      /* Enable the SSE and MMX builtins by default.  Don't enable MMX

> +         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to

> +        explicitly disable any of these.  In particular, disabling SSE

> +        and MMX for kernel code is extremely useful.  */

>        if (!ix86_arch_specified)

>        opts->x_ix86_isa_flags

> -       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX

> +       |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE

> +            | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)

> +               ? 0 : OPTION_MASK_ISA_MMX)

>              | TARGET_SUBTARGET64_ISA_DEFAULT)

>              & ~opts->x_ix86_isa_flags_explicit);


It looks to me that the above change is not needed at all if
__MMX_WITH_SSE__ is used in intrinsics headers. We have to be agnostic
to TARGET_MMX setting, the SSE2 alternatives in the instructions are
selected with  TARGET_MMX_WITH_SSE enables.

> @@ -4216,8 +4219,10 @@ ix86_option_override_internal (bool main_args_p,

>    if (!TARGET_80387_P (opts->x_target_flags))

>      opts->x_target_flags |= MASK_NO_FANCY_MATH_387;

>

> -  /* Turn on MMX builtins for -msse.  */

> -  if (TARGET_SSE_P (opts->x_ix86_isa_flags))

> +  /* Turn on MMX builtins for -msse.  Don't enable MMX ISA with

> +     TARGET_MMX_WITH_SSE.  */

> +  if (TARGET_SSE_P (opts->x_ix86_isa_flags)

> +      && !TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))

>      opts->x_ix86_isa_flags

>        |= OPTION_MASK_ISA_MMX & ~opts->x_ix86_isa_flags_explicit;


The above change is also not needed.

Uros.

>

> @@ -31769,14 +31774,17 @@ ix86_init_mmx_sse_builtins (void)

>                VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);

>

>    /* MMX access to the vec_init patterns.  */

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v2si",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_init_v2si",

>                      V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);

>

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v4hi",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_init_v4hi",

>                      V4HI_FTYPE_HI_HI_HI_HI,

>                      IX86_BUILTIN_VEC_INIT_V4HI);

>

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v8qi",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_init_v8qi",

>                      V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,

>                      IX86_BUILTIN_VEC_INIT_V8QI);

>

> @@ -31798,7 +31806,8 @@ ix86_init_mmx_sse_builtins (void)

>                      "__builtin_ia32_vec_ext_v4hi",

>                      HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);

>

> -  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_ext_v2si",

> +  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,

> +                    "__builtin_ia32_vec_ext_v2si",

>                      SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);

>

>    def_builtin_const (OPTION_MASK_ISA_SSE2, 0, "__builtin_ia32_vec_ext_v16qi",

> @@ -36931,6 +36940,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,

>         == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))

>        && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)

>      isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);

> +  /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when

> +     MMX is disabled.  */

> +  if (TARGET_MMX_WITH_SSE)

> +    {

> +      if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))

> +          == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))

> +         && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0)

> +       isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX);

> +      if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))

> +          == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))

> +         && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0)

> +       isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX);

> +      if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))

> +          == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))

> +         && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0)

> +       isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX);

> +    }

>    if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)

>      {

>        char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,

> diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h

> index 238b3df3121..7b613658111 100644

> --- a/gcc/config/i386/mmintrin.h

> +++ b/gcc/config/i386/mmintrin.h

> @@ -30,7 +30,7 @@

>  #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__

>  #pragma GCC push_options

>  #ifdef __x86_64__

> -#pragma GCC target("sse,mmx")

> +#pragma GCC target("sse2")

>  #else

>  #pragma GCC target("mmx")

>  #endif

> @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)

>  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

>  #ifndef __SSE2__

>  #pragma GCC push_options

> +#ifdef __x86_64__

> +#pragma GCC target("sse2")

> +#else

>  #pragma GCC target("sse2,mmx")

> +#endif

>  #define __DISABLE_SSE2__

>  #endif /* __SSE2__ */

>

> @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)

>  /* Add the 64-bit values in M1 to the 64-bit values in M2.  */

>  #ifndef __SSE2__

>  #pragma GCC push_options

> +#ifdef __x86_64__

> +#pragma GCC target("sse2")

> +#else

>  #pragma GCC target("sse2,mmx")

> +#endif

>  #define __DISABLE_SSE2__

>  #endif /* __SSE2__ */

>

> diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c b/gcc/testsuite/gcc.target/i386/pr82483-1.c

> index 59a59dc8dfe..b2028d8dc5e 100644

> --- a/gcc/testsuite/gcc.target/i386/pr82483-1.c

> +++ b/gcc/testsuite/gcc.target/i386/pr82483-1.c

> @@ -1,7 +1,7 @@

>  /* PR target/82483 */

>  /* { dg-do compile } */

>  /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */

> -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */

> +/* { dg-error "needs isa option" "" { target ia32 } 0 } */

>

>  #include <x86intrin.h>

>

> diff --git a/gcc/testsuite/gcc.target/i386/pr82483-2.c b/gcc/testsuite/gcc.target/i386/pr82483-2.c

> index 305ddbd6c64..c92de405cb3 100644

> --- a/gcc/testsuite/gcc.target/i386/pr82483-2.c

> +++ b/gcc/testsuite/gcc.target/i386/pr82483-2.c

> @@ -1,7 +1,7 @@

>  /* PR target/82483 */

>  /* { dg-do compile } */

>  /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */

> -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */

> +/* { dg-error "needs isa option" "" { target ia32 } 0 } */

>

>  #include <x86intrin.h>

>

> --

> 2.20.1

>

Patch

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 88005f4687f..10a9d631f29 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -100,7 +100,7 @@  BDESC (0, 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKN
 BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID)
 
 /* MMX */
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
 
 /* 3DNow! */
 BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
@@ -442,68 +442,68 @@  BDESC (0, 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNO
 BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
 
 /* MMX */
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
-
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
-BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
+
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
+BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
 
 /* 3DNow! */
 BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a9abbe8706b..1d417e08734 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4165,12 +4165,15 @@  ix86_option_override_internal (bool main_args_p,
       opts->x_target_flags
 	|= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
 
-      /* Enable by default the SSE and MMX builtins.  Do allow the user to
-	 explicitly disable any of these.  In particular, disabling SSE and
-	 MMX for kernel code is extremely useful.  */
+      /* Enable the SSE and MMX builtins by default.  Don't enable MMX
+         ISA with TARGET_MMX_WITH_SSE by default.  Do allow the user to
+	 explicitly disable any of these.  In particular, disabling SSE
+	 and MMX for kernel code is extremely useful.  */
       if (!ix86_arch_specified)
       opts->x_ix86_isa_flags
-	|= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
+	|= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
+	     | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
+		? 0 : OPTION_MASK_ISA_MMX)
 	     | TARGET_SUBTARGET64_ISA_DEFAULT)
             & ~opts->x_ix86_isa_flags_explicit);
 
@@ -4216,8 +4219,10 @@  ix86_option_override_internal (bool main_args_p,
   if (!TARGET_80387_P (opts->x_target_flags))
     opts->x_target_flags |= MASK_NO_FANCY_MATH_387;
 
-  /* Turn on MMX builtins for -msse.  */
-  if (TARGET_SSE_P (opts->x_ix86_isa_flags))
+  /* Turn on MMX builtins for -msse.  Don't enable MMX ISA with
+     TARGET_MMX_WITH_SSE.  */
+  if (TARGET_SSE_P (opts->x_ix86_isa_flags)
+      && !TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
     opts->x_ix86_isa_flags
       |= OPTION_MASK_ISA_MMX & ~opts->x_ix86_isa_flags_explicit;
 
@@ -31769,14 +31774,17 @@  ix86_init_mmx_sse_builtins (void)
 	       VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);
 
   /* MMX access to the vec_init patterns.  */
-  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v2si",
+  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
+		     "__builtin_ia32_vec_init_v2si",
 		     V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
 
-  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v4hi",
+  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
+		     "__builtin_ia32_vec_init_v4hi",
 		     V4HI_FTYPE_HI_HI_HI_HI,
 		     IX86_BUILTIN_VEC_INIT_V4HI);
 
-  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v8qi",
+  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
+		     "__builtin_ia32_vec_init_v8qi",
 		     V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
 		     IX86_BUILTIN_VEC_INIT_V8QI);
 
@@ -31798,7 +31806,8 @@  ix86_init_mmx_sse_builtins (void)
 		     "__builtin_ia32_vec_ext_v4hi",
 		     HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);
 
-  def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_ext_v2si",
+  def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
+		     "__builtin_ia32_vec_ext_v2si",
 		     SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);
 
   def_builtin_const (OPTION_MASK_ISA_SSE2, 0, "__builtin_ia32_vec_ext_v16qi",
@@ -36931,6 +36940,23 @@  ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
        == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
       && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
     isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
+  /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when
+     MMX is disabled.  */
+  if (TARGET_MMX_WITH_SSE)
+    {
+      if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
+	   == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
+	  && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0)
+	isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX);
+      if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
+	   == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
+	  && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0)
+	isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX);
+      if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
+	   == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
+	  && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0)
+	isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX);
+    }
   if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
     {
       char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,
diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
index 238b3df3121..7b613658111 100644
--- a/gcc/config/i386/mmintrin.h
+++ b/gcc/config/i386/mmintrin.h
@@ -30,7 +30,7 @@ 
 #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
 #pragma GCC push_options
 #ifdef __x86_64__
-#pragma GCC target("sse,mmx")
+#pragma GCC target("sse2")
 #else
 #pragma GCC target("mmx")
 #endif
@@ -315,7 +315,11 @@  _m_paddd (__m64 __m1, __m64 __m2)
 /* Add the 64-bit values in M1 to the 64-bit values in M2.  */
 #ifndef __SSE2__
 #pragma GCC push_options
+#ifdef __x86_64__
+#pragma GCC target("sse2")
+#else
 #pragma GCC target("sse2,mmx")
+#endif
 #define __DISABLE_SSE2__
 #endif /* __SSE2__ */
 
@@ -427,7 +431,11 @@  _m_psubd (__m64 __m1, __m64 __m2)
 /* Add the 64-bit values in M1 to the 64-bit values in M2.  */
 #ifndef __SSE2__
 #pragma GCC push_options
+#ifdef __x86_64__
+#pragma GCC target("sse2")
+#else
 #pragma GCC target("sse2,mmx")
+#endif
 #define __DISABLE_SSE2__
 #endif /* __SSE2__ */
 
diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c b/gcc/testsuite/gcc.target/i386/pr82483-1.c
index 59a59dc8dfe..b2028d8dc5e 100644
--- a/gcc/testsuite/gcc.target/i386/pr82483-1.c
+++ b/gcc/testsuite/gcc.target/i386/pr82483-1.c
@@ -1,7 +1,7 @@ 
 /* PR target/82483 */
 /* { dg-do compile } */
 /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */
-/* { dg-error "needs isa option" "" { target *-*-* } 0 } */
+/* { dg-error "needs isa option" "" { target ia32 } 0 } */
 
 #include <x86intrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/pr82483-2.c b/gcc/testsuite/gcc.target/i386/pr82483-2.c
index 305ddbd6c64..c92de405cb3 100644
--- a/gcc/testsuite/gcc.target/i386/pr82483-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr82483-2.c
@@ -1,7 +1,7 @@ 
 /* PR target/82483 */
 /* { dg-do compile } */
 /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */
-/* { dg-error "needs isa option" "" { target *-*-* } 0 } */
+/* { dg-error "needs isa option" "" { target ia32 } 0 } */
 
 #include <x86intrin.h>