[31/40] i386: Emulate MMX pshufb with SSE version

Message ID 20190214123031.13301-32-hjl.tools@gmail.com
State New
Headers show
Series
  • V5: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 14, 2019, 12:30 p.m.
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ...
	(ssse3_pshufbv8qi3_mmx): This.
	(ssse3_pshufbv8qi3): New.
	(ssse3_pshufbv8qi3_sse): Likewise.
---
 gcc/config/i386/sse.md | 56 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 54 insertions(+), 2 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 14, 2019, 2:20 p.m. | #1
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> Emulate MMX version of pshufb with SSE version by masking out the bit 3

> of the shuffle control byte.  Only SSE register source operand is allowed.

>

>         PR target/89021

>         * config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ...

>         (ssse3_pshufbv8qi3_mmx): This.

>         (ssse3_pshufbv8qi3): New.

>         (ssse3_pshufbv8qi3_sse): Likewise.


These insns can also be merged together using

 (clobber (match_scratch:V4SI 3 "=X,x,Yv"))

Uros.
> ---

>  gcc/config/i386/sse.md | 56 ++++++++++++++++++++++++++++++++++++++++--

>  1 file changed, 54 insertions(+), 2 deletions(-)

>

> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md

> index cc7dbe79fa7..a92505c54a1 100644

> --- a/gcc/config/i386/sse.md

> +++ b/gcc/config/i386/sse.md

> @@ -15722,18 +15722,70 @@

>     (set_attr "btver2_decode" "vector")

>     (set_attr "mode" "<sseinsnmode>")])

>

> -(define_insn "ssse3_pshufbv8qi3"

> +(define_expand "ssse3_pshufbv8qi3"

> +  [(set (match_operand:V8QI 0 "register_operand")

> +       (unspec:V8QI [(match_operand:V8QI 1 "register_operand")

> +                     (match_operand:V8QI 2 "nonimmediate_operand")]

> +                    UNSPEC_PSHUFB))]

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

> +{

> +  if (TARGET_MMX_WITH_SSE)

> +    {

> +      rtx op2 = force_reg (V8QImode, operands[2]);

> +      emit_insn (gen_ssse3_pshufbv8qi3_sse (operands[0], operands[1],

> +                                           op2));

> +      DONE;

> +    }

> +})

> +

> +(define_insn "ssse3_pshufbv8qi3_mmx"

>    [(set (match_operand:V8QI 0 "register_operand" "=y")

>         (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")

>                       (match_operand:V8QI 2 "nonimmediate_operand" "ym")]

>                      UNSPEC_PSHUFB))]

> -  "TARGET_SSSE3"

> +  "TARGET_SSSE3 && !TARGET_MMX_WITH_SSE"

>    "pshufb\t{%2, %0|%0, %2}";

>    [(set_attr "type" "sselog1")

>     (set_attr "prefix_extra" "1")

>     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))

>     (set_attr "mode" "DI")])

>

> +(define_insn_and_split "ssse3_pshufbv8qi3_sse"

> +  [(set (match_operand:V8QI 0 "register_operand" "=x,Yv")

> +       (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,Yv")

> +                     (match_operand:V8QI 2 "register_operand" "x,Yv")]

> +                    UNSPEC_PSHUFB))

> +   (clobber (match_scratch:V4SI 3 "=x,Yv"))]

> +  "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"

> +  "#"

> +  "reload_completed"

> +  [(set (match_dup 3) (match_dup 5))

> +   (set (match_dup 3)

> +       (and:V4SI (match_dup 3) (match_dup 2)))

> +   (set (match_dup 0)

> +       (unspec:V16QI [(match_dup 1) (match_dup 4)] UNSPEC_PSHUFB))]

> +{

> +  /* Emulate MMX version of pshufb with SSE version by masking out the

> +     bit 3 of the shuffle control byte.  */

> +  operands[0] = lowpart_subreg (V16QImode, operands[0],

> +                               GET_MODE (operands[0]));

> +  operands[1] = lowpart_subreg (V16QImode, operands[1],

> +                               GET_MODE (operands[1]));

> +  operands[2] = lowpart_subreg (V4SImode, operands[2],

> +                               GET_MODE (operands[2]));

> +  operands[4] = lowpart_subreg (V16QImode, operands[3],

> +                               GET_MODE (operands[3]));

> +  rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7),

> +                        GEN_INT (0xf7f7f7f7),

> +                        GEN_INT (0xf7f7f7f7),

> +                        GEN_INT (0xf7f7f7f7));

> +  rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par);

> +  operands[5] = force_const_mem (V4SImode, vec_const);

> +}

> +  [(set_attr "mmx_isa" "x64_noavx,x64_avx")

> +   (set_attr "type" "sselog1")

> +   (set_attr "mode" "TI,TI")])

> +

>  (define_insn "<ssse3_avx2>_psign<mode>3"

>    [(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x")

>         (unspec:VI124_AVX2

> --

> 2.20.1

>

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index cc7dbe79fa7..a92505c54a1 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15722,18 +15722,70 @@ 
    (set_attr "btver2_decode" "vector")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "ssse3_pshufbv8qi3"
+(define_expand "ssse3_pshufbv8qi3"
+  [(set (match_operand:V8QI 0 "register_operand")
+	(unspec:V8QI [(match_operand:V8QI 1 "register_operand")
+		      (match_operand:V8QI 2 "nonimmediate_operand")]
+		     UNSPEC_PSHUFB))]
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+{
+  if (TARGET_MMX_WITH_SSE)
+    {
+      rtx op2 = force_reg (V8QImode, operands[2]);
+      emit_insn (gen_ssse3_pshufbv8qi3_sse (operands[0], operands[1],
+					    op2));
+      DONE;
+    }
+})
+
+(define_insn "ssse3_pshufbv8qi3_mmx"
   [(set (match_operand:V8QI 0 "register_operand" "=y")
 	(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
 		      (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
 		     UNSPEC_PSHUFB))]
-  "TARGET_SSSE3"
+  "TARGET_SSSE3 && !TARGET_MMX_WITH_SSE"
   "pshufb\t{%2, %0|%0, %2}";
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
+(define_insn_and_split "ssse3_pshufbv8qi3_sse"
+  [(set (match_operand:V8QI 0 "register_operand" "=x,Yv")
+	(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,Yv")
+		      (match_operand:V8QI 2 "register_operand" "x,Yv")]
+		     UNSPEC_PSHUFB))
+   (clobber (match_scratch:V4SI 3 "=x,Yv"))]
+  "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
+  "#"
+  "reload_completed"
+  [(set (match_dup 3) (match_dup 5))
+   (set (match_dup 3)
+	(and:V4SI (match_dup 3) (match_dup 2)))
+   (set (match_dup 0)
+	(unspec:V16QI [(match_dup 1) (match_dup 4)] UNSPEC_PSHUFB))]
+{
+  /* Emulate MMX version of pshufb with SSE version by masking out the
+     bit 3 of the shuffle control byte.  */
+  operands[0] = lowpart_subreg (V16QImode, operands[0],
+				GET_MODE (operands[0]));
+  operands[1] = lowpart_subreg (V16QImode, operands[1],
+				GET_MODE (operands[1]));
+  operands[2] = lowpart_subreg (V4SImode, operands[2],
+				GET_MODE (operands[2]));
+  operands[4] = lowpart_subreg (V16QImode, operands[3],
+				GET_MODE (operands[3]));
+  rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7),
+			 GEN_INT (0xf7f7f7f7),
+			 GEN_INT (0xf7f7f7f7),
+			 GEN_INT (0xf7f7f7f7));
+  rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par);
+  operands[5] = force_const_mem (V4SImode, vec_const);
+}
+  [(set_attr "mmx_isa" "x64_noavx,x64_avx")
+   (set_attr "type" "sselog1")
+   (set_attr "mode" "TI,TI")])
+
 (define_insn "<ssse3_avx2>_psign<mode>3"
   [(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x")
 	(unspec:VI124_AVX2