[33/40] i386: Emulate MMX ssse3_palignrdi with SSE

Message ID 20190211225553.32050-34-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V4: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 11, 2019, 10:55 p.m.
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_palignrdi): Changed to
	define_insn_and_split to support SSE emulation.
---
 gcc/config/i386/sse.md | 54 ++++++++++++++++++++++++++++++++++--------
 1 file changed, 44 insertions(+), 10 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 12, 2019, 11:27 a.m. | #1
On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> Emulate MMX version of palignrq with SSE version by concatenating 2

> 64-bit MMX operands into a single 128-bit SSE operand, followed by

> SSE psrldq.  Only SSE register source operand is allowed.

>

>         PR target/89021

>         * config/i386/sse.md (ssse3_palignrdi): Changed to

>         define_insn_and_split to support SSE emulation.

> ---

>  gcc/config/i386/sse.md | 54 ++++++++++++++++++++++++++++++++++--------

>  1 file changed, 44 insertions(+), 10 deletions(-)

>

> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md

> index 15c187f7f5c..a1d43204344 100644

> --- a/gcc/config/i386/sse.md

> +++ b/gcc/config/i386/sse.md

> @@ -15977,23 +15977,57 @@

>     (set_attr "prefix" "orig,vex,evex")

>     (set_attr "mode" "<sseinsnmode>")])

>

> -(define_insn "ssse3_palignrdi"

> -  [(set (match_operand:DI 0 "register_operand" "=y")

> -       (unspec:DI [(match_operand:DI 1 "register_operand" "0")

> -                   (match_operand:DI 2 "nonimmediate_operand" "ym")

> -                   (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]

> +(define_insn_and_split "ssse3_palignrdi"

> +  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")

> +       (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")

> +                   (match_operand:DI 2 "nonimmediate_operand" "ym,x,Yv")

> +                   (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")]

>                    UNSPEC_PALIGNR))]

> -  "TARGET_SSSE3"

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

>  {

> -  operands[3] = GEN_INT (INTVAL (operands[3]) / 8);

> -  return "palignr\t{%3, %2, %0|%0, %2, %3}";

> +  if (TARGET_MMX_WITH_SSE)

> +    return "#";

> +  else

> +    {

> +      operands[3] = GEN_INT (INTVAL (operands[3]) / 8);

> +      return "palignr\t{%3, %2, %0|%0, %2, %3}";

> +    }


Use switch with "which_alternative" instead.

Uros.

>  }

> -  [(set_attr "type" "sseishft")

> +  "TARGET_MMX_WITH_SSE && reload_completed"

> +  [(set (match_dup 0)

> +       (lshiftrt:V1TI (match_dup 0) (match_dup 3)))]

> +{

> +  /* Emulate MMX palignrdi with SSE psrldq.  */

> +  rtx op0 = lowpart_subreg (V2DImode, operands[0],

> +                           GET_MODE (operands[0]));

> +  rtx insn;

> +  if (TARGET_AVX)

> +    insn = gen_vec_concatv2di (op0, operands[2], operands[1]);

> +  else

> +    {

> +      /* NB: SSE can only concatenate OP0 and OP1 to OP0.  */

> +      insn = gen_vec_concatv2di (op0, operands[1], operands[2]);

> +      emit_insn (insn);

> +      /* Swap bits 0:63 with bits 64:127.  */

> +      rtx mask = gen_rtx_PARALLEL (VOIDmode,

> +                                  gen_rtvec (4, GEN_INT (2),

> +                                             GEN_INT (3),

> +                                             GEN_INT (0),

> +                                             GEN_INT (1)));

> +      rtx op1 = gen_rtx_REG (V4SImode, REGNO (op0));


lowpart_subreg.

Uros.
> +      rtx op2 = gen_rtx_VEC_SELECT (V4SImode, op1, mask);

> +      insn = gen_rtx_SET (op1, op2);

> +    }

> +  emit_insn (insn);

> +  operands[0] = lowpart_subreg (V1TImode, op0, GET_MODE (op0));

> +}

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "sseishft")

>     (set_attr "atom_unit" "sishuf")

>     (set_attr "prefix_extra" "1")

>     (set_attr "length_immediate" "1")

>     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))

> -   (set_attr "mode" "DI")])

> +   (set_attr "mode" "DI,TI,TI")])

>

>  ;; Mode iterator to handle singularity w/ absence of V2DI and V4DI

>  ;; modes for abs instruction on pre AVX-512 targets.

> --

> 2.20.1

>

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 15c187f7f5c..a1d43204344 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15977,23 +15977,57 @@ 
    (set_attr "prefix" "orig,vex,evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "ssse3_palignrdi"
-  [(set (match_operand:DI 0 "register_operand" "=y")
-	(unspec:DI [(match_operand:DI 1 "register_operand" "0")
-		    (match_operand:DI 2 "nonimmediate_operand" "ym")
-		    (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
+(define_insn_and_split "ssse3_palignrdi"
+  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
+	(unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
+		    (match_operand:DI 2 "nonimmediate_operand" "ym,x,Yv")
+		    (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")]
 		   UNSPEC_PALIGNR))]
-  "TARGET_SSSE3"
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
 {
-  operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-  return "palignr\t{%3, %2, %0|%0, %2, %3}";
+  if (TARGET_MMX_WITH_SSE)
+    return "#";
+  else
+    {
+      operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
+      return "palignr\t{%3, %2, %0|%0, %2, %3}";
+    }
 }
-  [(set_attr "type" "sseishft")
+  "TARGET_MMX_WITH_SSE && reload_completed"
+  [(set (match_dup 0)
+	(lshiftrt:V1TI (match_dup 0) (match_dup 3)))]
+{
+  /* Emulate MMX palignrdi with SSE psrldq.  */
+  rtx op0 = lowpart_subreg (V2DImode, operands[0],
+			    GET_MODE (operands[0]));
+  rtx insn;
+  if (TARGET_AVX)
+    insn = gen_vec_concatv2di (op0, operands[2], operands[1]);
+  else
+    {
+      /* NB: SSE can only concatenate OP0 and OP1 to OP0.  */
+      insn = gen_vec_concatv2di (op0, operands[1], operands[2]);
+      emit_insn (insn);
+      /* Swap bits 0:63 with bits 64:127.  */
+      rtx mask = gen_rtx_PARALLEL (VOIDmode,
+				   gen_rtvec (4, GEN_INT (2),
+					      GEN_INT (3),
+					      GEN_INT (0),
+					      GEN_INT (1)));
+      rtx op1 = gen_rtx_REG (V4SImode, REGNO (op0));
+      rtx op2 = gen_rtx_VEC_SELECT (V4SImode, op1, mask);
+      insn = gen_rtx_SET (op1, op2);
+    }
+  emit_insn (insn);
+  operands[0] = lowpart_subreg (V1TImode, op0, GET_MODE (op0));
+}
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "sseishft")
    (set_attr "atom_unit" "sishuf")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 ;; Mode iterator to handle singularity w/ absence of V2DI and V4DI
 ;; modes for abs instruction on pre AVX-512 targets.