[08/40] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE

Message ID 20190211225553.32050-9-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V4: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 11, 2019, 10:55 p.m.
Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE.  Only SSE register
source operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_ashr<mode>3): Changed to define_expand.
	Disallow TARGET_MMX_WITH_SSE.
	(mmx_<shift_insn><mode>3): Likewise.
	(ashr<mode>3): New.
	(*ashr<mode>3): Likewise.
	(<shift_insn><mode>3): Likewise.
	(*<shift_insn><mode>3): Likewise.
---
 gcc/config/i386/mmx.md | 68 ++++++++++++++++++++++++++++++++----------
 1 file changed, 52 insertions(+), 16 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 11, 2019, 11:15 p.m. | #1
On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>

> Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE.  Only SSE register

> source operand is allowed.

>

>         PR target/89021

>         * config/i386/mmx.md (mmx_ashr<mode>3): Changed to define_expand.

>         Disallow TARGET_MMX_WITH_SSE.

>         (mmx_<shift_insn><mode>3): Likewise.

>         (ashr<mode>3): New.

>         (*ashr<mode>3): Likewise.

>         (<shift_insn><mode>3): Likewise.

>         (*<shift_insn><mode>3): Likewise.

> ---

>  gcc/config/i386/mmx.md | 68 ++++++++++++++++++++++++++++++++----------

>  1 file changed, 52 insertions(+), 16 deletions(-)

>

> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> index 0e44b3ce9b8..1b4f67be902 100644

> --- a/gcc/config/i386/mmx.md

> +++ b/gcc/config/i386/mmx.md

> @@ -983,33 +983,69 @@

>    [(set_attr "type" "mmxadd")

>     (set_attr "mode" "DI")])

>

> -(define_insn "mmx_ashr<mode>3"

> -  [(set (match_operand:MMXMODE24 0 "register_operand" "=y")

> +(define_expand "mmx_ashr<mode>3"

> +  [(set (match_operand:MMXMODE24 0 "register_operand")

>          (ashiftrt:MMXMODE24

> -         (match_operand:MMXMODE24 1 "register_operand" "0")

> -         (match_operand:DI 2 "nonmemory_operand" "yN")))]

> -  "TARGET_MMX"

> -  "psra<mmxvecsize>\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "mmxshft")

> +         (match_operand:MMXMODE24 1 "register_operand")

> +         (match_operand:DI 2 "nonmemory_operand")))]

> +  "TARGET_MMX && !TARGET_MMX_WITH_SSE")


Are you sure this is the correct condition? This pattern is called
from a builtin, which should be enabled for TARGET_MMX *or*
TARGET_MMX_WITH_SSE.

Please review other builtins enable conditions for this issue.

Uros.

> +(define_expand "ashr<mode>3"

> +  [(set (match_operand:MMXMODE24 0 "register_operand")

> +        (ashiftrt:MMXMODE24

> +         (match_operand:MMXMODE24 1 "register_operand")

> +         (match_operand:DI 2 "nonmemory_operand")))]

> +  "TARGET_MMX_WITH_SSE")

> +

> +(define_insn "*ashr<mode>3"

> +  [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv")

> +        (ashiftrt:MMXMODE24

> +         (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv")

> +         (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]

> +  "TARGET_MMX || TARGET_MMX_WITH_SSE"

> +  "@

> +   psra<mmxvecsize>\t{%2, %0|%0, %2}

> +   psra<mmxvecsize>\t{%2, %0|%0, %2}

> +   vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "mmxshft,sseishft,sseishft")

>     (set (attr "length_immediate")

>       (if_then_else (match_operand 2 "const_int_operand")

>         (const_string "1")

>         (const_string "0")))

> -   (set_attr "mode" "DI")])

> +   (set_attr "mode" "DI,TI,TI")])

>

> -(define_insn "mmx_<shift_insn><mode>3"

> -  [(set (match_operand:MMXMODE248 0 "register_operand" "=y")

> +(define_expand "mmx_<shift_insn><mode>3"

> +  [(set (match_operand:MMXMODE248 0 "register_operand")

>          (any_lshift:MMXMODE248

> -         (match_operand:MMXMODE248 1 "register_operand" "0")

> -         (match_operand:DI 2 "nonmemory_operand" "yN")))]

> -  "TARGET_MMX"

> -  "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "mmxshft")

> +         (match_operand:MMXMODE248 1 "register_operand")

> +         (match_operand:DI 2 "nonmemory_operand")))]

> +  "TARGET_MMX && !TARGET_MMX_WITH_SSE")

> +

> +(define_expand "<shift_insn><mode>3"

> +  [(set (match_operand:MMXMODE248 0 "register_operand")

> +        (any_lshift:MMXMODE248

> +         (match_operand:MMXMODE248 1 "register_operand")

> +         (match_operand:DI 2 "nonmemory_operand")))]

> +  "TARGET_MMX_WITH_SSE")

> +

> +(define_insn "*<shift_insn><mode>3"

> +  [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv")

> +        (any_lshift:MMXMODE248

> +         (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv")

> +         (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]

> +  "TARGET_MMX || TARGET_MMX_WITH_SSE"

> +  "@

> +   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}

> +   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}

> +   vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "mmxshft,sseishft,sseishft")

>     (set (attr "length_immediate")

>       (if_then_else (match_operand 2 "const_int_operand")

>         (const_string "1")

>         (const_string "0")))

> -   (set_attr "mode" "DI")])

> +   (set_attr "mode" "DI,TI,TI")])

>

>  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

>  ;;

> --

> 2.20.1

>
Uros Bizjak Feb. 11, 2019, 11:35 p.m. | #2
On Tue, Feb 12, 2019 at 12:15 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.tools@gmail.com> wrote:

> >

> > Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE.  Only SSE register

> > source operand is allowed.

> >

> >         PR target/89021

> >         * config/i386/mmx.md (mmx_ashr<mode>3): Changed to define_expand.

> >         Disallow TARGET_MMX_WITH_SSE.

> >         (mmx_<shift_insn><mode>3): Likewise.

> >         (ashr<mode>3): New.

> >         (*ashr<mode>3): Likewise.

> >         (<shift_insn><mode>3): Likewise.

> >         (*<shift_insn><mode>3): Likewise.

> > ---

> >  gcc/config/i386/mmx.md | 68 ++++++++++++++++++++++++++++++++----------

> >  1 file changed, 52 insertions(+), 16 deletions(-)

> >

> > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> > index 0e44b3ce9b8..1b4f67be902 100644

> > --- a/gcc/config/i386/mmx.md

> > +++ b/gcc/config/i386/mmx.md

> > @@ -983,33 +983,69 @@

> >    [(set_attr "type" "mmxadd")

> >     (set_attr "mode" "DI")])

> >

> > -(define_insn "mmx_ashr<mode>3"

> > -  [(set (match_operand:MMXMODE24 0 "register_operand" "=y")

> > +(define_expand "mmx_ashr<mode>3"

> > +  [(set (match_operand:MMXMODE24 0 "register_operand")

> >          (ashiftrt:MMXMODE24

> > -         (match_operand:MMXMODE24 1 "register_operand" "0")

> > -         (match_operand:DI 2 "nonmemory_operand" "yN")))]

> > -  "TARGET_MMX"

> > -  "psra<mmxvecsize>\t{%2, %0|%0, %2}"

> > -  [(set_attr "type" "mmxshft")

> > +         (match_operand:MMXMODE24 1 "register_operand")

> > +         (match_operand:DI 2 "nonmemory_operand")))]

> > +  "TARGET_MMX && !TARGET_MMX_WITH_SSE")

>

> Are you sure this is the correct condition? This pattern is called

> from a builtin, which should be enabled for TARGET_MMX *or*

> TARGET_MMX_WITH_SSE.


It looks to me that "TARGET_MMX || TARGET_MMX_WITH_SSE" should be used
with mmx_* patterns (and new SSE constraints should be added to these
patterns) and new named shift expanders should be added here.

Uros.

> > +(define_expand "ashr<mode>3"

> > +  [(set (match_operand:MMXMODE24 0 "register_operand")

> > +        (ashiftrt:MMXMODE24

> > +         (match_operand:MMXMODE24 1 "register_operand")

> > +         (match_operand:DI 2 "nonmemory_operand")))]

> > +  "TARGET_MMX_WITH_SSE")

> > +

> > +(define_insn "*ashr<mode>3"

> > +  [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv")

> > +        (ashiftrt:MMXMODE24

> > +         (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv")

> > +         (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]

> > +  "TARGET_MMX || TARGET_MMX_WITH_SSE"

> > +  "@

> > +   psra<mmxvecsize>\t{%2, %0|%0, %2}

> > +   psra<mmxvecsize>\t{%2, %0|%0, %2}

> > +   vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"

> > +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> > +   (set_attr "type" "mmxshft,sseishft,sseishft")

> >     (set (attr "length_immediate")

> >       (if_then_else (match_operand 2 "const_int_operand")

> >         (const_string "1")

> >         (const_string "0")))

> > -   (set_attr "mode" "DI")])

> > +   (set_attr "mode" "DI,TI,TI")])

> >

> > -(define_insn "mmx_<shift_insn><mode>3"

> > -  [(set (match_operand:MMXMODE248 0 "register_operand" "=y")

> > +(define_expand "mmx_<shift_insn><mode>3"

> > +  [(set (match_operand:MMXMODE248 0 "register_operand")

> >          (any_lshift:MMXMODE248

> > -         (match_operand:MMXMODE248 1 "register_operand" "0")

> > -         (match_operand:DI 2 "nonmemory_operand" "yN")))]

> > -  "TARGET_MMX"

> > -  "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"

> > -  [(set_attr "type" "mmxshft")

> > +         (match_operand:MMXMODE248 1 "register_operand")

> > +         (match_operand:DI 2 "nonmemory_operand")))]

> > +  "TARGET_MMX && !TARGET_MMX_WITH_SSE")

> > +

> > +(define_expand "<shift_insn><mode>3"

> > +  [(set (match_operand:MMXMODE248 0 "register_operand")

> > +        (any_lshift:MMXMODE248

> > +         (match_operand:MMXMODE248 1 "register_operand")

> > +         (match_operand:DI 2 "nonmemory_operand")))]

> > +  "TARGET_MMX_WITH_SSE")

> > +

> > +(define_insn "*<shift_insn><mode>3"

> > +  [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv")

> > +        (any_lshift:MMXMODE248

> > +         (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv")

> > +         (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]

> > +  "TARGET_MMX || TARGET_MMX_WITH_SSE"

> > +  "@

> > +   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}

> > +   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}

> > +   vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"

> > +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> > +   (set_attr "type" "mmxshft,sseishft,sseishft")

> >     (set (attr "length_immediate")

> >       (if_then_else (match_operand 2 "const_int_operand")

> >         (const_string "1")

> >         (const_string "0")))

> > -   (set_attr "mode" "DI")])

> > +   (set_attr "mode" "DI,TI,TI")])

> >

> >  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

> >  ;;

> > --

> > 2.20.1

> >

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 0e44b3ce9b8..1b4f67be902 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -983,33 +983,69 @@ 
   [(set_attr "type" "mmxadd")
    (set_attr "mode" "DI")])
 
-(define_insn "mmx_ashr<mode>3"
-  [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
+(define_expand "mmx_ashr<mode>3"
+  [(set (match_operand:MMXMODE24 0 "register_operand")
         (ashiftrt:MMXMODE24
-	  (match_operand:MMXMODE24 1 "register_operand" "0")
-	  (match_operand:DI 2 "nonmemory_operand" "yN")))]
-  "TARGET_MMX"
-  "psra<mmxvecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxshft")
+	  (match_operand:MMXMODE24 1 "register_operand")
+	  (match_operand:DI 2 "nonmemory_operand")))]
+  "TARGET_MMX && !TARGET_MMX_WITH_SSE")
+
+(define_expand "ashr<mode>3"
+  [(set (match_operand:MMXMODE24 0 "register_operand")
+        (ashiftrt:MMXMODE24
+	  (match_operand:MMXMODE24 1 "register_operand")
+	  (match_operand:DI 2 "nonmemory_operand")))]
+  "TARGET_MMX_WITH_SSE")
+
+(define_insn "*ashr<mode>3"
+  [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv")
+        (ashiftrt:MMXMODE24
+	  (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv")
+	  (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+  "@
+   psra<mmxvecsize>\t{%2, %0|%0, %2}
+   psra<mmxvecsize>\t{%2, %0|%0, %2}
+   vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxshft,sseishft,sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand")
        (const_string "1")
        (const_string "0")))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
-(define_insn "mmx_<shift_insn><mode>3"
-  [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
+(define_expand "mmx_<shift_insn><mode>3"
+  [(set (match_operand:MMXMODE248 0 "register_operand")
         (any_lshift:MMXMODE248
-	  (match_operand:MMXMODE248 1 "register_operand" "0")
-	  (match_operand:DI 2 "nonmemory_operand" "yN")))]
-  "TARGET_MMX"
-  "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxshft")
+	  (match_operand:MMXMODE248 1 "register_operand")
+	  (match_operand:DI 2 "nonmemory_operand")))]
+  "TARGET_MMX && !TARGET_MMX_WITH_SSE")
+
+(define_expand "<shift_insn><mode>3"
+  [(set (match_operand:MMXMODE248 0 "register_operand")
+        (any_lshift:MMXMODE248
+	  (match_operand:MMXMODE248 1 "register_operand")
+	  (match_operand:DI 2 "nonmemory_operand")))]
+  "TARGET_MMX_WITH_SSE")
+
+(define_insn "*<shift_insn><mode>3"
+  [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv")
+        (any_lshift:MMXMODE248
+	  (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv")
+	  (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+  "@
+   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
+   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
+   vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxshft,sseishft,sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand")
        (const_string "1")
        (const_string "0")))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;