[32/43] i386: Emulate MMX ssse3_psign<mode>3 with SSE

Message ID 20190210001947.27278-33-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V3: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 10, 2019, 12:19 a.m.
Emulate MMX ssse3_psign<mode>3 with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation.
---
 gcc/config/i386/sse.md | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 10, 2019, 12:29 p.m. | #1
On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX ssse3_psign<mode>3 with SSE.  Only SSE register source operand

> is allowed.

>

> 	PR target/89021

> 	* config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation.


OK.

Uros.

> ---

>  gcc/config/i386/sse.md | 18 +++++++++++-------

>  1 file changed, 11 insertions(+), 7 deletions(-)

>

> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md

> index 00e1fe03995..c3dcb6bc6b1 100644

> --- a/gcc/config/i386/sse.md

> +++ b/gcc/config/i386/sse.md

> @@ -15908,17 +15908,21 @@

>     (set_attr "mode" "<sseinsnmode>")])

>

>  (define_insn "ssse3_psign<mode>3"

> -  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")

> +  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv")

>  	(unspec:MMXMODEI

> -	  [(match_operand:MMXMODEI 1 "register_operand" "0")

> -	   (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]

> +	  [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv")

> +	   (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym,x,Yv")]

>  	  UNSPEC_PSIGN))]

> -  "TARGET_SSSE3"

> -  "psign<mmxvecsize>\t{%2, %0|%0, %2}";

> -  [(set_attr "type" "sselog1")

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

> +  "@

> +   psign<mmxvecsize>\t{%2, %0|%0, %2}

> +   psign<mmxvecsize>\t{%2, %0|%0, %2}

> +   vpsign<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "sselog1")

>     (set_attr "prefix_extra" "1")

>     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p

> (insn)"))

> -   (set_attr "mode" "DI")])

> +   (set_attr "mode" "DI,TI,TI")])

>

>  (define_insn "<ssse3_avx2>_palignr<mode>_mask"

>    [(set (match_operand:VI1_AVX512 0 "register_operand" "=v")

> --

> 2.20.1

>

>

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 00e1fe03995..c3dcb6bc6b1 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15908,17 +15908,21 @@ 
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "ssse3_psign<mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv")
 	(unspec:MMXMODEI
-	  [(match_operand:MMXMODEI 1 "register_operand" "0")
-	   (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
+	  [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv")
+	   (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym,x,Yv")]
 	  UNSPEC_PSIGN))]
-  "TARGET_SSSE3"
-  "psign<mmxvecsize>\t{%2, %0|%0, %2}";
-  [(set_attr "type" "sselog1")
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+  "@
+   psign<mmxvecsize>\t{%2, %0|%0, %2}
+   psign<mmxvecsize>\t{%2, %0|%0, %2}
+   vpsign<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "<ssse3_avx2>_palignr<mode>_mask"
   [(set (match_operand:VI1_AVX512 0 "register_operand" "=v")