[18/43] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE

Message ID 20190210001947.27278-19-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V3: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 10, 2019, 12:19 a.m.
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_<code>v4hi3): Add SSE emulation
	support.
	(mmx_<code>v8qi3): Likewise.
	(smaxmin:<code>v4hi3): New.
	(umaxmin:<code>v8qi3): Likewise.
	(smaxmin:*mmx_<code>v4hi3): Add SSE emulation.
	(umaxmin:*mmx_<code>v8qi3): Likewise.
---
 gcc/config/i386/mmx.md | 60 +++++++++++++++++++++++++++++++-----------
 1 file changed, 44 insertions(+), 16 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 10, 2019, 11:36 a.m. | #1
On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE.  Only SSE register source

> operand is allowed.

>

> 	PR target/89021

> 	* config/i386/mmx.md (mmx_<code>v4hi3): Add SSE emulation

> 	support.

> 	(mmx_<code>v8qi3): Likewise.

> 	(smaxmin:<code>v4hi3): New.

> 	(umaxmin:<code>v8qi3): Likewise.

> 	(smaxmin:*mmx_<code>v4hi3): Add SSE emulation.

> 	(umaxmin:*mmx_<code>v8qi3): Likewise.


Please change insn conditions, as in previous patch.

Uros.

> ---

>  gcc/config/i386/mmx.md | 60 +++++++++++++++++++++++++++++++-----------

>  1 file changed, 44 insertions(+), 16 deletions(-)

>

> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> index 5265024c529..3390e42ea5b 100644

> --- a/gcc/config/i386/mmx.md

> +++ b/gcc/config/i386/mmx.md

> @@ -957,38 +957,66 @@

>          (smaxmin:V4HI

>  	  (match_operand:V4HI 1 "nonimmediate_operand")

>  	  (match_operand:V4HI 2 "nonimmediate_operand")))]

> -  "TARGET_SSE || TARGET_3DNOW_A"

> +  "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)

> +   || TARGET_3DNOW_A"

> +  "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")

> +

> +(define_expand "<code>v4hi3"

> +  [(set (match_operand:V4HI 0 "register_operand")

> +        (smaxmin:V4HI

> +	  (match_operand:V4HI 1 "nonimmediate_operand")

> +	  (match_operand:V4HI 2 "nonimmediate_operand")))]

> +  "TARGET_MMX_WITH_SSE"

>    "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")

>

>  (define_insn "*mmx_<code>v4hi3"

> -  [(set (match_operand:V4HI 0 "register_operand" "=y")

> +  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")

>          (smaxmin:V4HI

> -	  (match_operand:V4HI 1 "nonimmediate_operand" "%0")

> -	  (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]

> -  "(TARGET_SSE || TARGET_3DNOW_A)

> +	  (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yv")

> +	  (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")))]

> +  "(((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)

> +    || TARGET_3DNOW_A)

>     && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"

> -  "p<maxmin_int>w\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "mmxadd")

> -   (set_attr "mode" "DI")])

> +  "@

> +   p<maxmin_int>w\t{%2, %0|%0, %2}

> +   p<maxmin_int>w\t{%2, %0|%0, %2}

> +   vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "mmxadd,sseiadd,sseiadd")

> +   (set_attr "mode" "DI,TI,TI")])

>

>  (define_expand "mmx_<code>v8qi3"

>    [(set (match_operand:V8QI 0 "register_operand")

>          (umaxmin:V8QI

>  	  (match_operand:V8QI 1 "nonimmediate_operand")

>  	  (match_operand:V8QI 2 "nonimmediate_operand")))]

> -  "TARGET_SSE || TARGET_3DNOW_A"

> +  "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)

> +   || TARGET_3DNOW_A"

> +  "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")

> +

> +(define_expand "<code>v8qi3"

> +  [(set (match_operand:V8QI 0 "register_operand")

> +        (umaxmin:V8QI

> +	  (match_operand:V8QI 1 "nonimmediate_operand")

> +	  (match_operand:V8QI 2 "nonimmediate_operand")))]

> +  "TARGET_MMX_WITH_SSE"

>    "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")

>

>  (define_insn "*mmx_<code>v8qi3"

> -  [(set (match_operand:V8QI 0 "register_operand" "=y")

> +  [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")

>          (umaxmin:V8QI

> -	  (match_operand:V8QI 1 "nonimmediate_operand" "%0")

> -	  (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]

> -  "(TARGET_SSE || TARGET_3DNOW_A)

> +	  (match_operand:V8QI 1 "nonimmediate_operand" "%0,0,Yv")

> +	  (match_operand:V8QI 2 "nonimmediate_operand" "ym,x,Yv")))]

> +  "(((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)

> +    || TARGET_3DNOW_A)

>     && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"

> -  "p<maxmin_int>b\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "mmxadd")

> -   (set_attr "mode" "DI")])

> +  "@

> +   p<maxmin_int>b\t{%2, %0|%0, %2}

> +   p<maxmin_int>b\t{%2, %0|%0, %2}

> +   vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "mmxadd,sseiadd,sseiadd")

> +   (set_attr "mode" "DI,TI,TI")])

>

>  (define_insn "mmx_ashr<mode>3"

>    [(set (match_operand:MMXMODE24 0 "register_operand" "=y")

> --

> 2.20.1

>

>

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 5265024c529..3390e42ea5b 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -957,38 +957,66 @@ 
         (smaxmin:V4HI
 	  (match_operand:V4HI 1 "nonimmediate_operand")
 	  (match_operand:V4HI 2 "nonimmediate_operand")))]
-  "TARGET_SSE || TARGET_3DNOW_A"
+  "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)
+   || TARGET_3DNOW_A"
+  "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
+
+(define_expand "<code>v4hi3"
+  [(set (match_operand:V4HI 0 "register_operand")
+        (smaxmin:V4HI
+	  (match_operand:V4HI 1 "nonimmediate_operand")
+	  (match_operand:V4HI 2 "nonimmediate_operand")))]
+  "TARGET_MMX_WITH_SSE"
   "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
 
 (define_insn "*mmx_<code>v4hi3"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
+  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
         (smaxmin:V4HI
-	  (match_operand:V4HI 1 "nonimmediate_operand" "%0")
-	  (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
-  "(TARGET_SSE || TARGET_3DNOW_A)
+	  (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yv")
+	  (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")))]
+  "(((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)
+    || TARGET_3DNOW_A)
    && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
-  "p<maxmin_int>w\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxadd")
-   (set_attr "mode" "DI")])
+  "@
+   p<maxmin_int>w\t{%2, %0|%0, %2}
+   p<maxmin_int>w\t{%2, %0|%0, %2}
+   vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxadd,sseiadd,sseiadd")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_<code>v8qi3"
   [(set (match_operand:V8QI 0 "register_operand")
         (umaxmin:V8QI
 	  (match_operand:V8QI 1 "nonimmediate_operand")
 	  (match_operand:V8QI 2 "nonimmediate_operand")))]
-  "TARGET_SSE || TARGET_3DNOW_A"
+  "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)
+   || TARGET_3DNOW_A"
+  "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
+
+(define_expand "<code>v8qi3"
+  [(set (match_operand:V8QI 0 "register_operand")
+        (umaxmin:V8QI
+	  (match_operand:V8QI 1 "nonimmediate_operand")
+	  (match_operand:V8QI 2 "nonimmediate_operand")))]
+  "TARGET_MMX_WITH_SSE"
   "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
 
 (define_insn "*mmx_<code>v8qi3"
-  [(set (match_operand:V8QI 0 "register_operand" "=y")
+  [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")
         (umaxmin:V8QI
-	  (match_operand:V8QI 1 "nonimmediate_operand" "%0")
-	  (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
-  "(TARGET_SSE || TARGET_3DNOW_A)
+	  (match_operand:V8QI 1 "nonimmediate_operand" "%0,0,Yv")
+	  (match_operand:V8QI 2 "nonimmediate_operand" "ym,x,Yv")))]
+  "(((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)
+    || TARGET_3DNOW_A)
    && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
-  "p<maxmin_int>b\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxadd")
-   (set_attr "mode" "DI")])
+  "@
+   p<maxmin_int>b\t{%2, %0|%0, %2}
+   p<maxmin_int>b\t{%2, %0|%0, %2}
+   vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxadd,sseiadd,sseiadd")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "mmx_ashr<mode>3"
   [(set (match_operand:MMXMODE24 0 "register_operand" "=y")