[19/43] i386: Emulate MMX mmx_pmovmskb with SSE

Message ID 20190210001947.27278-20-hjl.tools@gmail.com
State New
Headers show
Series
  • V3: Emulate MMX intrinsics with SSE
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Commit Message

H.J. Lu Feb. 10, 2019, 12:19 a.m.
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pmovmskb): Changed to
	define_insn_and_split to support SSE emulation.
---
 gcc/config/i386/mmx.md | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 10, 2019, 12:11 p.m. | #1
On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb

> from QImode to SImode.  Only SSE register source operand is allowed.

>

> 	PR target/89021

> 	* config/i386/mmx.md (mmx_pmovmskb): Changed to

> 	define_insn_and_split to support SSE emulation.

> ---

>  gcc/config/i386/mmx.md | 32 +++++++++++++++++++++++++-------

>  1 file changed, 25 insertions(+), 7 deletions(-)

>

> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> index 3390e42ea5b..0d00896127b 100644

> --- a/gcc/config/i386/mmx.md

> +++ b/gcc/config/i386/mmx.md

> @@ -1761,14 +1761,32 @@

>    [(set_attr "type" "mmxshft")

>     (set_attr "mode" "DI")])

>

> -(define_insn "mmx_pmovmskb"

> -  [(set (match_operand:SI 0 "register_operand" "=r")

> -	(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]

> +(define_insn_and_split "mmx_pmovmskb"

> +  [(set (match_operand:SI 0 "register_operand" "=r,r")

> +	(unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")]

>  		   UNSPEC_MOVMSK))]

> -  "TARGET_SSE || TARGET_3DNOW_A"

> -  "pmovmskb\t{%1, %0|%0, %1}"

> -  [(set_attr "type" "mmxcvt")

> -   (set_attr "mode" "DI")])

> +  "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)

> +   || TARGET_3DNOW_A"


Please change insn condition ...

> +  "@

> +   pmovmskb\t{%1, %0|%0, %1}

> +   #"

> +  "&& reload_completed && TARGET_MMX_WITH_SSE"


... and split condition ...

> +  [(const_int 0)]

> +{

> +  /* Generate SSE pmovmskb.  */

> +  rtx op0 = operands[0];

> +  rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]));

> +  rtx insn = gen_sse2_pmovmskb (op0, op1);

> +  emit_insn (insn);

> +  /* Zero-extend from QImode to SImode.  */

> +  op1 = gen_rtx_REG (QImode, REGNO (operands[0]));

> +  insn = gen_zero_extendqisi2 (op0, op1);

> +  emit_insn (insn);

> +  DONE;


... and explicitily write RTX instead of (const_int 0).

Uros.

> +}

> +  [(set_attr "mmx_isa" "native,x64")

> +   (set_attr "type" "mmxcvt,ssemov")

> +   (set_attr "mode" "DI,TI")])

>

>  (define_expand "mmx_maskmovq"

>    [(set (match_operand:V8QI 0 "memory_operand")

> --

> 2.20.1

>

>

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 3390e42ea5b..0d00896127b 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1761,14 +1761,32 @@ 
   [(set_attr "type" "mmxshft")
    (set_attr "mode" "DI")])
 
-(define_insn "mmx_pmovmskb"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
+(define_insn_and_split "mmx_pmovmskb"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")]
 		   UNSPEC_MOVMSK))]
-  "TARGET_SSE || TARGET_3DNOW_A"
-  "pmovmskb\t{%1, %0|%0, %1}"
-  [(set_attr "type" "mmxcvt")
-   (set_attr "mode" "DI")])
+  "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE)
+   || TARGET_3DNOW_A"
+  "@
+   pmovmskb\t{%1, %0|%0, %1}
+   #"
+  "&& reload_completed && TARGET_MMX_WITH_SSE"
+  [(const_int 0)]
+{
+  /* Generate SSE pmovmskb.  */
+  rtx op0 = operands[0];
+  rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]));
+  rtx insn = gen_sse2_pmovmskb (op0, op1);
+  emit_insn (insn);
+  /* Zero-extend from QImode to SImode.  */
+  op1 = gen_rtx_REG (QImode, REGNO (operands[0]));
+  insn = gen_zero_extendqisi2 (op0, op1);
+  emit_insn (insn);
+  DONE;
+}
+  [(set_attr "mmx_isa" "native,x64")
+   (set_attr "type" "mmxcvt,ssemov")
+   (set_attr "mode" "DI,TI")])
 
 (define_expand "mmx_maskmovq"
   [(set (match_operand:V8QI 0 "memory_operand")