[28/43] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE

Message ID 20190210001947.27278-29-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V3: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 10, 2019, 12:19 a.m.
Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3):
	Changed to define_insn_and_split to support SSE emulation.
---
 gcc/config/i386/sse.md | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 10, 2019, 12:23 p.m. | #1
On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits

> 64:95 to bits 32:63 in SSE register.  Only SSE register source operand

> is allowed.

>

> 	PR target/89021

> 	* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3):

> 	Changed to define_insn_and_split to support SSE emulation.

> ---

>  gcc/config/i386/sse.md | 32 ++++++++++++++++++++++++--------

>  1 file changed, 24 insertions(+), 8 deletions(-)

>

> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md

> index 6138f59f267..4bcfd3fc272 100644

> --- a/gcc/config/i386/sse.md

> +++ b/gcc/config/i386/sse.md

> @@ -15480,26 +15480,42 @@

>     (set_attr "prefix" "orig,vex")

>     (set_attr "mode" "TI")])

>

> -(define_insn "ssse3_ph<plusminus_mnemonic>dv2si3"

> -  [(set (match_operand:V2SI 0 "register_operand" "=y")

> +(define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"

> +  [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")

>  	(vec_concat:V2SI

>  	  (plusminus:SI

>  	    (vec_select:SI

> -	      (match_operand:V2SI 1 "register_operand" "0")

> +	      (match_operand:V2SI 1 "register_operand" "0,0,Yv")

>  	      (parallel [(const_int 0)]))

>  	    (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))

>  	  (plusminus:SI

>  	    (vec_select:SI

> -	      (match_operand:V2SI 2 "nonimmediate_operand" "ym")

> +	      (match_operand:V2SI 2 "nonimmediate_operand" "ym,x,Yv")

>  	      (parallel [(const_int 0)]))

>  	    (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]

> -  "TARGET_SSSE3"

> -  "ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "sseiadd")

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

> +  "@

> +   ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}

> +   #

> +   #"

> +  "&& reload_completed && TARGET_MMX_WITH_SSE"


Please fix split condition.

Uros.

> +  [(const_int 0)]

> +{

> +  /* Generate SSE version of the operation.  */

> +  rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));

> +  rtx op1 = gen_rtx_REG (V4SImode, REGNO (operands[1]));

> +  rtx op2 = gen_rtx_REG (V4SImode, REGNO (operands[2]));

> +  rtx insn = gen_ssse3_ph<plusminus_mnemonic>dv4si3 (op0, op1, op2);

> +  emit_insn (insn);

> +  ix86_move_vector_high_sse_to_mmx (op0);

> +  DONE;

> +}

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "sseiadd")

>     (set_attr "atom_unit" "complex")

>     (set_attr "prefix_extra" "1")

>     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p

> (insn)"))

> -   (set_attr "mode" "DI")])

> +   (set_attr "mode" "DI,TI,TI")])

>

>  (define_insn "avx2_pmaddubsw256"

>    [(set (match_operand:V16HI 0 "register_operand" "=x,v")

> --

> 2.20.1

>

>

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6138f59f267..4bcfd3fc272 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15480,26 +15480,42 @@ 
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
-(define_insn "ssse3_ph<plusminus_mnemonic>dv2si3"
-  [(set (match_operand:V2SI 0 "register_operand" "=y")
+(define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"
+  [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
 	(vec_concat:V2SI
 	  (plusminus:SI
 	    (vec_select:SI
-	      (match_operand:V2SI 1 "register_operand" "0")
+	      (match_operand:V2SI 1 "register_operand" "0,0,Yv")
 	      (parallel [(const_int 0)]))
 	    (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
 	  (plusminus:SI
 	    (vec_select:SI
-	      (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+	      (match_operand:V2SI 2 "nonimmediate_operand" "ym,x,Yv")
 	      (parallel [(const_int 0)]))
 	    (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
-  "TARGET_SSSE3"
-  "ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseiadd")
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+  "@
+   ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
+   #
+   #"
+  "&& reload_completed && TARGET_MMX_WITH_SSE"
+  [(const_int 0)]
+{
+  /* Generate SSE version of the operation.  */
+  rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
+  rtx op1 = gen_rtx_REG (V4SImode, REGNO (operands[1]));
+  rtx op2 = gen_rtx_REG (V4SImode, REGNO (operands[2]));
+  rtx insn = gen_ssse3_ph<plusminus_mnemonic>dv4si3 (op0, op1, op2);
+  emit_insn (insn);
+  ix86_move_vector_high_sse_to_mmx (op0);
+  DONE;
+}
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "avx2_pmaddubsw256"
   [(set (match_operand:V16HI 0 "register_operand" "=x,v")