[06/43] i386: Emulate MMX smulv4hi3_highpart with SSE

Message ID 20190210001947.27278-7-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V3: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 10, 2019, 12:19 a.m.
Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
	TARGET_MMX_WITH_SSE.
	(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
	SSE support.
---
 gcc/config/i386/mmx.md | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 10, 2019, 10:18 a.m. | #1
On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is

> allowed.

>

> 	PR target/89021

> 	* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow

> 	TARGET_MMX_WITH_SSE.

> 	(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add

> 	SSE support.


OK.

Uros.

> ---

>  gcc/config/i386/mmx.md | 21 +++++++++++++--------

>  1 file changed, 13 insertions(+), 8 deletions(-)

>

> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> index e3b3ab09012..82ca8719492 100644

> --- a/gcc/config/i386/mmx.md

> +++ b/gcc/config/i386/mmx.md

> @@ -784,23 +784,28 @@

>  	      (sign_extend:V4SI

>  		(match_operand:V4HI 2 "nonimmediate_operand")))

>  	    (const_int 16))))]

> -  "TARGET_MMX"

> +  "TARGET_MMX || TARGET_MMX_WITH_SSE"

>    "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")

>

>  (define_insn "*mmx_smulv4hi3_highpart"

> -  [(set (match_operand:V4HI 0 "register_operand" "=y")

> +  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")

>  	(truncate:V4HI

>  	  (lshiftrt:V4SI

>  	    (mult:V4SI

>  	      (sign_extend:V4SI

> -		(match_operand:V4HI 1 "nonimmediate_operand" "%0"))

> +		(match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yv"))

>  	      (sign_extend:V4SI

> -		(match_operand:V4HI 2 "nonimmediate_operand" "ym")))

> +		(match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")))

>  	    (const_int 16))))]

> -  "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"

> -  "pmulhw\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "mmxmul")

> -   (set_attr "mode" "DI")])

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE)

> +   && ix86_binary_operator_ok (MULT, V4HImode, operands)"

> +  "@

> +   pmulhw\t{%2, %0|%0, %2}

> +   pmulhw\t{%2, %0|%0, %2}

> +   vpmulhw\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "mmxmul,ssemul,ssemul")

> +   (set_attr "mode" "DI,TI,TI")])

>

>  (define_expand "mmx_umulv4hi3_highpart"

>    [(set (match_operand:V4HI 0 "register_operand")

> --

> 2.20.1

>

>

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index e3b3ab09012..82ca8719492 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -784,23 +784,28 @@ 
 	      (sign_extend:V4SI
 		(match_operand:V4HI 2 "nonimmediate_operand")))
 	    (const_int 16))))]
-  "TARGET_MMX"
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 
 (define_insn "*mmx_smulv4hi3_highpart"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
+  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
 	(truncate:V4HI
 	  (lshiftrt:V4SI
 	    (mult:V4SI
 	      (sign_extend:V4SI
-		(match_operand:V4HI 1 "nonimmediate_operand" "%0"))
+		(match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yv"))
 	      (sign_extend:V4SI
-		(match_operand:V4HI 2 "nonimmediate_operand" "ym")))
+		(match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")))
 	    (const_int 16))))]
-  "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
-  "pmulhw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+  "@
+   pmulhw\t{%2, %0|%0, %2}
+   pmulhw\t{%2, %0|%0, %2}
+   vpmulhw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxmul,ssemul,ssemul")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_umulv4hi3_highpart"
   [(set (match_operand:V4HI 0 "register_operand")