[05/43] i386: Emulate MMX mulv4hi3 with SSE

Message ID 20190209132352.1828-6-hjl.tools@gmail.com
State Superseded
Headers show
Series
  • V2: Emulate MMX intrinsics with SSE
Related show

Commit Message

H.J. Lu Feb. 9, 2019, 1:23 p.m.
Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mulv4hi3): New.
	(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE.  Add SSE
	support.
---
 gcc/config/i386/mmx.md | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

-- 
2.20.1

Comments

Uros Bizjak Feb. 10, 2019, 10:17 a.m. | #1
On 2/9/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is

> allowed.

>

> 	PR target/89021

> 	* config/i386/mmx.md (mulv4hi3): New.

> 	(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE.  Add SSE

> 	support.


OK.

Uros.

> ---

>  gcc/config/i386/mmx.md | 26 +++++++++++++++++++-------

>  1 file changed, 19 insertions(+), 7 deletions(-)

>

> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md

> index 01a71aa128b..2712a86ea3c 100644

> --- a/gcc/config/i386/mmx.md

> +++ b/gcc/config/i386/mmx.md

> @@ -753,14 +753,26 @@

>    "TARGET_MMX"

>    "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")

>

> +(define_expand "mulv4hi3"

> +  [(set (match_operand:V4HI 0 "register_operand")

> +        (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand")

> +		   (match_operand:V4HI 2 "nonimmediate_operand")))]

> +  "TARGET_MMX_WITH_SSE"

> +  "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")

> +

>  (define_insn "*mmx_mulv4hi3"

> -  [(set (match_operand:V4HI 0 "register_operand" "=y")

> -        (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")

> -		   (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]

> -  "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"

> -  "pmullw\t{%2, %0|%0, %2}"

> -  [(set_attr "type" "mmxmul")

> -   (set_attr "mode" "DI")])

> +  [(set (match_operand:V4HI 0 "register_operand" "=y,Yx,Yy")

> +        (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yy")

> +		   (match_operand:V4HI 2 "nonimmediate_operand" "ym,Yx,Yy")))]

> +  "(TARGET_MMX || TARGET_MMX_WITH_SSE)

> +   && ix86_binary_operator_ok (MULT, V4HImode, operands)"

> +  "@

> +   pmullw\t{%2, %0|%0, %2}

> +   pmullw\t{%2, %0|%0, %2}

> +   vpmullw\t{%2, %1, %0|%0, %1, %2}"

> +  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")

> +   (set_attr "type" "mmxmul,ssemul,ssemul")

> +   (set_attr "mode" "DI,TI,TI")])

>

>  (define_expand "mmx_smulv4hi3_highpart"

>    [(set (match_operand:V4HI 0 "register_operand")

> --

> 2.20.1

>

>

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 01a71aa128b..2712a86ea3c 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -753,14 +753,26 @@ 
   "TARGET_MMX"
   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 
+(define_expand "mulv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand")
+        (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand")
+		   (match_operand:V4HI 2 "nonimmediate_operand")))]
+  "TARGET_MMX_WITH_SSE"
+  "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
+
 (define_insn "*mmx_mulv4hi3"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
-        (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
-		   (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
-  "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
-  "pmullw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  [(set (match_operand:V4HI 0 "register_operand" "=y,Yx,Yy")
+        (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yy")
+		   (match_operand:V4HI 2 "nonimmediate_operand" "ym,Yx,Yy")))]
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+  "@
+   pmullw\t{%2, %0|%0, %2}
+   pmullw\t{%2, %0|%0, %2}
+   vpmullw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxmul,ssemul,ssemul")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_smulv4hi3_highpart"
   [(set (match_operand:V4HI 0 "register_operand")