[Arm] Backport hlt to all architectures.

Message ID 20190207154937.GA32201@arm.com
State New
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Series
  • [Arm] Backport hlt to all architectures.
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Commit Message

Tamar Christina Feb. 7, 2019, 3:49 p.m.
Hi All,

The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64.  In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment.  This requires that HLT also be backported to all earlier
architectures.  The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].

The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].

[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e

build on native hardware and regtested on
  arm-none-elf, arm-none-elf (32 bit host),
  arm-none-linux-gnueabihf, arm-none-linux-gnueabihf (32 bit host)

Cross-compiled and regtested on
  arm-none-linux-gnueabihf, armeb-none-elf, arm-wince-pe

and no issues.


Ok for master? and for backport to binutils-2.32?

Thanks,
Tamar

gas/ChangeLog:

2019-02-07  Tamar Christina  <tamar.christina@arm.com>

	* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
	hlt to armv1.
	* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
	* testsuite/gas/arm/hlt.d: New test.
	* testsuite/gas/arm/hlt.s: New test.

opcodes/ChangeLog:

2019-02-07  Tamar Christina  <tamar.christina@arm.com>

	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.

--

Comments

Nick Clifton Feb. 7, 2019, 4:18 p.m. | #1
Hi Tamar,

> The Arm Architectural Reference Manual [1] doesn't explicitly mention this


Is this going to change in a future update to the ARM ?  If not, then I think
that it would be worth including a comment in the sources explaining that whilst
the support for a HLT instruction for pre v8 architectures might look like an
error, it is in fact correct.

> Ok for master? 


Yes, approved.

> and for backport to binutils-2.32?


Also approved.

Cheers
  Nick
Tamar Christina Feb. 7, 2019, 4:32 p.m. | #2
Hi Nick,

> 

> > The Arm Architectural Reference Manual [1] doesn't explicitly mention

> > this

> 

> Is this going to change in a future update to the ARM ?  If not, then I think

> that it would be worth including a comment in the sources explaining that

> whilst the support for a HLT instruction for pre v8 architectures might look

> like an error, it is in fact correct.


I've asked for a note, however I don't know how likely this is as the Arm ARM
no longer shows which architectures an instruction is available in.  In the mean
time I'll add a comment in the source.

Thanks,
Tamar

Patch

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 81b5ceedcc9dba5a8d0309731f03108e3853d3d8..ed500772bcfab7d8fd4464a681e76ab0b32c5c1a 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -20187,11 +20187,18 @@  static const struct asm_opcode insns[] =
 #define THUMB_VARIANT & arm_ext_v8
 
  tCE("sevl",	320f005, _sevl,    0, (),		noargs,	t_hint),
- TUE("hlt",	1000070, ba80,     1, (oIffffb),	bkpt,	t_hlt),
  TCE("ldaexd",	1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
 							ldrexd, t_ldrexd),
  TCE("stlexd",	1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
 							strexd, t_strexd),
+
+/* Defined in V8 but is in NOP space so available to all arch.  */
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_v1
+#undef  ARM_VARIANT
+#define ARM_VARIANT  & arm_ext_v1
+ TUE("hlt",	1000070, ba80,     1, (oIffffb),	bkpt,	t_hlt),
+
  /* ARMv8 T32 only.  */
 #undef  ARM_VARIANT
 #define ARM_VARIANT  NULL
diff --git a/gas/testsuite/gas/arm/armv8a-automatic-hlt.d b/gas/testsuite/gas/arm/armv8a-automatic-hlt.d
index ee6c428538f8616f2d0a48f3e2ed35b0f6d8a002..9ce94d36c92d8cd1d9daa50088a1d9fb9f4ddccd 100644
--- a/gas/testsuite/gas/arm/armv8a-automatic-hlt.d
+++ b/gas/testsuite/gas/arm/armv8a-automatic-hlt.d
@@ -5,4 +5,6 @@  Attribute Section: aeabi
 File Attributes
   Tag_CPU_arch: v8
   Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
   Tag_THUMB_ISA_use: Thumb-2
+
diff --git a/gas/testsuite/gas/arm/hlt.d b/gas/testsuite/gas/arm/hlt.d
new file mode 100644
index 0000000000000000000000000000000000000000..b05c1fb8d64786f46a859304762f9aecf2ca702f
--- /dev/null
+++ b/gas/testsuite/gas/arm/hlt.d
@@ -0,0 +1,35 @@ 
+#objdump: -d
+# This test is only valid on ELF based ports.
+#notarget: *-*-pe *-*-wince
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:\s+ba80      	hlt	0x0000
+[^:]+:\s+ba8f      	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+ba80      	hlt	0x0000
+[^:]+:\s+ba8f      	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+ba80      	hlt	0x0000
+[^:]+:\s+ba8f      	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+ba80      	hlt	0x0000
+[^:]+:\s+ba8f      	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+ba80      	hlt	0x0000
+[^:]+:\s+ba8f      	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
+[^:]+:\s+e1000070 	hlt	0x0000
+[^:]+:\s+e100007f 	hlt	0x000f
diff --git a/gas/testsuite/gas/arm/hlt.s b/gas/testsuite/gas/arm/hlt.s
new file mode 100644
index 0000000000000000000000000000000000000000..02d1316bcac85c83b436ba6ed0f89fd71291f581
--- /dev/null
+++ b/gas/testsuite/gas/arm/hlt.s
@@ -0,0 +1,22 @@ 
+# Test that hlt is available for all architectures.
+.macro gen_for_arch arch, has_thumb
+	.arch \arch
+	.ifc "yes","\has_thumb"
+	.thumb
+	hlt
+	hlt 0xf
+	.endif
+	.arm
+	hlt
+	hlt 0xf
+.endm
+
+gen_for_arch armv8-a, yes
+gen_for_arch armv7-a, yes
+gen_for_arch armv6, yes
+gen_for_arch armv5t, yes
+gen_for_arch armv4t, yes
+gen_for_arch armv3, no
+gen_for_arch armv2, no
+gen_for_arch armv1, no
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 488522770f8a6b5932cb68f3cd64c1a3c63db3f2..71d7c524a22b0d93e5b0dd1573abbe158cd636e8 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1788,7 +1788,8 @@  static const struct opcode32 arm_opcodes[] =
   /* V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x0320f005, 0x0fffffff, "sevl"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  /* Defined in V8 but is in NOP space so available to all arch.  */
+  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},