[AArch64,2/3] Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.

Message ID 5C4AD7FF.1050003@foss.arm.com
State New
Headers show
Series
  • Make changes to the Armv8.5-A Memory Tagging Extension support
Related show

Commit Message

Kyrill Tkachov Jan. 25, 2019, 9:33 a.m.
Hi

This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction.

STGZM Xt, [<Xn|SP>]

For ease of review I have not added the regenerated files in the patch. I
will add those in my final commit.

Builds and reg tests all pass on aarch64-none-elf.

Is this ok for trunk?

Thanks
Sudi

*** gas/ChangeLog ***

2019-01-25  Sudakshina Das  <sudi.das@arm.com>

     * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
     * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
     * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
     * testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

2019-01-25  Sudakshina Das  <sudi.das@arm.com>

     * aarch64-asm-2.c: Regenerated.
     * aarch64-dis-2.c: Likewise.
     * aarch64-opc-2.c: Likewise.
     * aarch64-tbl.h (aarch64_opcode): Add new stzgm.

Comments

Nick Clifton Jan. 25, 2019, 1:50 p.m. | #1
Hi Kyrill,

> Is this ok for trunk?


> *** gas/ChangeLog ***

> 2019-01-25  Sudakshina Das  <sudi.das@arm.com>

> 

>     * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.

>     * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

>     * testsuite/gas/aarch64/illegal-memtag.l: Likewise.

>     * testsuite/gas/aarch64/illegal-memtag.s: Likewise.

> 

> *** opcodes/ChangeLog ***

> 2019-01-25  Sudakshina Das  <sudi.das@arm.com>

> 

>     * aarch64-asm-2.c: Regenerated.

>     * aarch64-dis-2.c: Likewise.

>     * aarch64-opc-2.c: Likewise.

>     * aarch64-tbl.h (aarch64_opcode): Add new stzgm.


Approved - please apply.

Cheers
  Nick

Patch

diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index 363bbe2eb3b1da373737c7d6efce9eba3b6bb6a1..678fefce6096a9f72c36065c908abde6aa7da021 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -121,3 +121,9 @@  Disassembly of section \.text:
 .*:	d960001f 	ldg	xzr, \[x0\]
 .*:	d96ff000 	ldg	x0, \[x0, #4080\]
 .*:	d9700000 	ldg	x0, \[x0, #-4096\]
+.*:	d9200000 	stzgm	x0, \[x0\]
+.*:	d920001b 	stzgm	x27, \[x0\]
+.*:	d9200360 	stzgm	x0, \[x27\]
+.*:	d9200379 	stzgm	x25, \[x27\]
+.*:	d92003e0 	stzgm	x0, \[sp\]
+.*:	d920001f 	stzgm	xzr, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 62c9436d78fea63a8ac45126c5f85416a1487822..b8cab9f0eff727d0d5da9c25745f441885babf58 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -30,6 +30,15 @@  func:
 	\op [sp], #-4096
 	.endm
 
+	.macro expand_ldg_bulk op
+	\op x0, [x0]
+	\op x27, [x0]
+	\op x0, [x27]
+	\op x25, [x27]
+	\op x0, [sp]
+	\op xzr, [x0]
+	.endm
+
 	# IRG
 	expand_3_reg irg
 	irg sp, x0
@@ -98,3 +107,5 @@  func:
 	ldg xzr, [x0, #0]
 	ldg x0, [x0, #4080]
 	ldg x0, [x0, #-4096]
+
+	expand_ldg_bulk stzgm
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index dfdf00aba1ea3e21c29ca602de30336b3f00859b..2505ffe79f80b693eb27c2c5da6d4f7384b703f4 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -12,6 +12,8 @@ 
 [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
 [^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
 [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
+[^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `stzgm x2,\[x3,#16\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `stzgm x4,\[x5,#16\]!'
 [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
 [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
 [^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -37,3 +39,5 @@ 
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
 [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzgm x0,\[xzr\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 35d1b12870bee105ede52d86b392afc68c8190d0..2a45e164af3847f18c441e9cc45d7b79c865404f 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -20,6 +20,10 @@  func:
 	stgp x1, x2, [x3, #33]
 	stgp x1, x2, [x3, #-1025]
 
+	# STZGM
+	stzgm x2, [x3, #16]
+	stzgm x4, [x5, #16]!
+
 	# Illegal SP/XZR registers
 	irg xzr, x2, x3
 	irg x1, xzr, x3
@@ -46,3 +50,5 @@  func:
 	stgp x0, x0, [xzr]
 	ldg sp, [x0, #16]
 	ldg x0, [xzr, #16]
+	stzgm x0, [xzr]
+	stzgm sp, [x3]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index d4ecd6df42033cf05a333e81890c602c1ae7e2a6..277293b40c9d85026400afbfe5a5183f6fa5cf3e 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3324,6 +3324,7 @@  struct aarch64_opcode aarch64_opcode_table[] =
   RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
   RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
   RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
+  MEMTAG_INSN ("stzgm", 0xd9200000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
   /* Limited Ordering Regions load/store instructions.  */
   _LOR_INSN ("ldlar",  0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL,       F_GPRSIZE_IN_Q),
   _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),