[Arm] Fix FPU configurations for Cortex-R7 and Cortex-R8

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State New
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  • [Arm] Fix FPU configurations for Cortex-R7 and Cortex-R8
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Commit Message

Andre Vieira (lists) Nov. 27, 2018, 2:10 p.m.
Hi,

This patch fixes the FPU configurations of Cortex-R7 and Cortex-R8,
enabling the use of FP16 conversion instructions for both and adding the
option to disable double precision instruction support using '+nofp.dp'.

Passes the self-check during building for an arm target.

Is this OK for trunk?

And could I also backport this to GCC-8?

gcc/ChangeLog:
2018-11-27  Andre Vieira  <andre.simoesdiasvieira@arm.com>

        * config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.
        (cortex-r8, cortex-r7): Update default and add new configuration.

Comments

Richard Earnshaw (lists) Nov. 27, 2018, 2:18 p.m. | #1
On 27/11/2018 14:10, Andre Vieira (lists) wrote:
> 

> Hi,

> 

> This patch fixes the FPU configurations of Cortex-R7 and Cortex-R8,

> enabling the use of FP16 conversion instructions for both and adding the

> option to disable double precision instruction support using '+nofp.dp'.

> 

> Passes the self-check during building for an arm target.

> 

> Is this OK for trunk?

> 

> And could I also backport this to GCC-8?

> 

> gcc/ChangeLog:

> 2018-11-27  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>         * config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.

>         (cortex-r8, cortex-r7): Update default and add new configuration.

> 

> 

> 0001-Arm-Fix-fpu-configurations-for-Cortex-R7-and-Cortex-.patch

> 

> From 9878f38a3de6001e8876d21f03adbb7ebf551a79 Mon Sep 17 00:00:00 2001

> From: Andre Vieira <andre.simoesdiasvieira@arm.com>

> Date: Mon, 26 Nov 2018 16:48:46 +0000

> Subject: [PATCH] [Arm] Fix fpu configurations for Cortex-R7 and Cortex-R8

> 

> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have

> SP only and SP + DP configurations.


You're missing the updates to the documentation.

R.

> ---

>  gcc/config/arm/arm-cpus.in | 8 ++++++--

>  1 file changed, 6 insertions(+), 2 deletions(-)

> 

> diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in

> index c71409e5dd9bcad525ed98cefd839bed0fd6f8ee..2fed508a46bc138caaac5d9905d8955e29eb7097 100644

> --- a/gcc/config/arm/arm-cpus.in

> +++ b/gcc/config/arm/arm-cpus.in

> @@ -476,6 +476,8 @@ begin arch armv7-r

>   optalias vfpv3xd fp.sp

>   option fp add VFPv3 FP_DBL

>   optalias vfpv3-d16 fp

> + option vfpv3xd-fp16 add VFPv3 fp16conv

> + option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv

>   option idiv add adiv

>   option nofp remove ALL_FP

>   option noidiv remove adiv

> @@ -1086,7 +1088,8 @@ end cpu cortex-r5

>  begin cpu cortex-r7

>   cname cortexr7

>   tune flags LDSCHED

> - architecture armv7-r+idiv+fp

> + architecture armv7-r+idiv+vfpv3-d16-fp16

> + option nofp.dp remove FP_DBL

>   option nofp remove ALL_FP

>   costs cortex

>   vendor 41

> @@ -1097,7 +1100,8 @@ begin cpu cortex-r8

>   cname cortexr8

>   tune for cortex-r7

>   tune flags LDSCHED

> - architecture armv7-r+idiv+fp

> + architecture armv7-r+idiv+vfpv3-d16-fp16

> + option nofp.dp remove FP_DBL

>   option nofp remove ALL_FP

>   costs cortex

>   vendor 41

>
Andre Vieira (lists) Nov. 28, 2018, 10:43 a.m. | #2
On 27/11/18 14:18, Richard Earnshaw (lists) wrote:
> On 27/11/2018 14:10, Andre Vieira (lists) wrote:

>>

>> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have

>> SP only and SP + DP configurations.

> 

> You're missing the updates to the documentation.

> 

> R.

> 

Oops.

Here are the documentation bits I forgot, I've also opened  PR 88224 in
bugzilla for this issue.

Is this OK for trunk and gcc-8 backport?

gcc/ChangeLog:
2018-11-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>

        PR target/88224
        * config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.
        (cortex-r7, cortex-r8): Update default and add new configuration.
        * doc/invoke.texi (armv7-r): Add two new vfp options.
        (nofp.dp): Add cortex-r7 and cortex-r8 to the list of targets that
        support this option.
From 6116856e3f948bcb23ee6ecf9b7b94204d7f45af Mon Sep 17 00:00:00 2001
From: Andre Vieira <andre.simoesdiasvieira@arm.com>

Date: Mon, 26 Nov 2018 16:48:46 +0000
Subject: [PATCH] [Arm] Fix fpu configurations for Cortex-R7 and Cortex-R8

Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have
SP only and SP + DP configurations.
---
 gcc/config/arm/arm-cpus.in |  8 ++++++--
 gcc/doc/invoke.texi        | 11 ++++++++++-
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index c71409e5dd9bcad525ed98cefd839bed0fd6f8ee..2fed508a46bc138caaac5d9905d8955e29eb7097 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -476,6 +476,8 @@ begin arch armv7-r
  optalias vfpv3xd fp.sp
  option fp add VFPv3 FP_DBL
  optalias vfpv3-d16 fp
+ option vfpv3xd-fp16 add VFPv3 fp16conv
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
  option idiv add adiv
  option nofp remove ALL_FP
  option noidiv remove adiv
@@ -1086,7 +1088,8 @@ end cpu cortex-r5
 begin cpu cortex-r7
  cname cortexr7
  tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
  vendor 41
@@ -1097,7 +1100,8 @@ begin cpu cortex-r8
  cname cortexr8
  tune for cortex-r7
  tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
  vendor 41
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 755a00017f71a04cee1742dca8c57172573a87fa..2ddddad52d928660b6c034f1c90e5c45f12d7a76 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16827,6 +16827,14 @@ The single-precision VFPv3 floating-point instructions.  The extension
 The VFPv3 floating-point instructions with 16 double-precision registers.
 The extension +vfpv3-d16 can be used as an alias for this extension.
 
+@item +vfpv3xd-d16-fp16
+The single-precision VFPv3 floating-point instructions with 16 double-precision
+registers and the half-precision floating-point conversion operations.
+
+@item +vfpv3-d16-fp16
+The VFPv3 floating-point instructions, with 16 double-precision
+registers and the half-precision floating-point conversion operations.
+
 @item +nofp
 Disable the floating-point extension.
 
@@ -17014,7 +17022,8 @@ Disables the floating-point and SIMD instructions on
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions
-on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.
+on @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52} and
+@samp{cortex-m7}.
 
 @item +nosimd
 Disables the SIMD (but not floating-point) instructions on
-- 
1.9.1
Richard Earnshaw (lists) Nov. 28, 2018, 10:57 a.m. | #3
On 28/11/2018 10:43, Andre Vieira (lists) wrote:
> On 27/11/18 14:18, Richard Earnshaw (lists) wrote:

>> On 27/11/2018 14:10, Andre Vieira (lists) wrote:

>>>

>>> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have

>>> SP only and SP + DP configurations.

>>

>> You're missing the updates to the documentation.

>>

>> R.

>>

> Oops.

> 

> Here are the documentation bits I forgot, I've also opened  PR 88224 in

> bugzilla for this issue.

> 

> Is this OK for trunk and gcc-8 backport?


Yes, this is OK for both.

R.

> 

> gcc/ChangeLog:

> 2018-11-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>         PR target/88224

>         * config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.

>         (cortex-r7, cortex-r8): Update default and add new configuration.

>         * doc/invoke.texi (armv7-r): Add two new vfp options.

>         (nofp.dp): Add cortex-r7 and cortex-r8 to the list of targets that

>         support this option.

> 

> 

> 

> 0001-Arm-Fix-fpu-configurations-for-Cortex-R7-and-Cortex-.patch

> 

> From 6116856e3f948bcb23ee6ecf9b7b94204d7f45af Mon Sep 17 00:00:00 2001

> From: Andre Vieira <andre.simoesdiasvieira@arm.com>

> Date: Mon, 26 Nov 2018 16:48:46 +0000

> Subject: [PATCH] [Arm] Fix fpu configurations for Cortex-R7 and Cortex-R8

> 

> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have

> SP only and SP + DP configurations.

> ---

>  gcc/config/arm/arm-cpus.in |  8 ++++++--

>  gcc/doc/invoke.texi        | 11 ++++++++++-

>  2 files changed, 16 insertions(+), 3 deletions(-)

> 

> diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in

> index c71409e5dd9bcad525ed98cefd839bed0fd6f8ee..2fed508a46bc138caaac5d9905d8955e29eb7097 100644

> --- a/gcc/config/arm/arm-cpus.in

> +++ b/gcc/config/arm/arm-cpus.in

> @@ -476,6 +476,8 @@ begin arch armv7-r

>   optalias vfpv3xd fp.sp

>   option fp add VFPv3 FP_DBL

>   optalias vfpv3-d16 fp

> + option vfpv3xd-fp16 add VFPv3 fp16conv

> + option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv

>   option idiv add adiv

>   option nofp remove ALL_FP

>   option noidiv remove adiv

> @@ -1086,7 +1088,8 @@ end cpu cortex-r5

>  begin cpu cortex-r7

>   cname cortexr7

>   tune flags LDSCHED

> - architecture armv7-r+idiv+fp

> + architecture armv7-r+idiv+vfpv3-d16-fp16

> + option nofp.dp remove FP_DBL

>   option nofp remove ALL_FP

>   costs cortex

>   vendor 41

> @@ -1097,7 +1100,8 @@ begin cpu cortex-r8

>   cname cortexr8

>   tune for cortex-r7

>   tune flags LDSCHED

> - architecture armv7-r+idiv+fp

> + architecture armv7-r+idiv+vfpv3-d16-fp16

> + option nofp.dp remove FP_DBL

>   option nofp remove ALL_FP

>   costs cortex

>   vendor 41

> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi

> index 755a00017f71a04cee1742dca8c57172573a87fa..2ddddad52d928660b6c034f1c90e5c45f12d7a76 100644

> --- a/gcc/doc/invoke.texi

> +++ b/gcc/doc/invoke.texi

> @@ -16827,6 +16827,14 @@ The single-precision VFPv3 floating-point instructions.  The extension

>  The VFPv3 floating-point instructions with 16 double-precision registers.

>  The extension +vfpv3-d16 can be used as an alias for this extension.

>  

> +@item +vfpv3xd-d16-fp16

> +The single-precision VFPv3 floating-point instructions with 16 double-precision

> +registers and the half-precision floating-point conversion operations.

> +

> +@item +vfpv3-d16-fp16

> +The VFPv3 floating-point instructions, with 16 double-precision

> +registers and the half-precision floating-point conversion operations.

> +

>  @item +nofp

>  Disable the floating-point extension.

>  

> @@ -17014,7 +17022,8 @@ Disables the floating-point and SIMD instructions on

>  

>  @item +nofp.dp

>  Disables the double-precision component of the floating-point instructions

> -on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.

> +on @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52} and

> +@samp{cortex-m7}.

>  

>  @item +nosimd

>  Disables the SIMD (but not floating-point) instructions on

>
Andre Vieira (lists) Nov. 29, 2018, 10:21 a.m. | #4
On 28/11/18 10:57, Richard Earnshaw (lists) wrote:
> On 28/11/2018 10:43, Andre Vieira (lists) wrote:

>> On 27/11/18 14:18, Richard Earnshaw (lists) wrote:

>>> On 27/11/2018 14:10, Andre Vieira (lists) wrote:

>>>>

>>>> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have

>>>> SP only and SP + DP configurations.

>>>

>>> You're missing the updates to the documentation.

>>>

>>> R.

>>>

>> Oops.

>>

>> Here are the documentation bits I forgot, I've also opened  PR 88224 in

>> bugzilla for this issue.

>>

>> Is this OK for trunk and gcc-8 backport?

> 

> Yes, this is OK for both.

Committed this to trunk, I'll commit the backport next week.
> 

> R.

>
Gerald Pfeifer Dec. 27, 2018, 12:57 a.m. | #5
On Wed, 28 Nov 2018, Andre Vieira (lists) wrote:
> Here are the documentation bits I forgot, I've also opened  PR 88224 in

> bugzilla for this issue.

> 

> Is this OK for trunk and gcc-8 backport?

> 

> gcc/ChangeLog:

> 2018-11-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>         PR target/88224

>         * config/arm/arm-cpus.in (armv7-r): Add FP16conv configurations.

>         (cortex-r7, cortex-r8): Update default and add new configuration.

>         * doc/invoke.texi (armv7-r): Add two new vfp options.

>         (nofp.dp): Add cortex-r7 and cortex-r8 to the list of targets that

>         support this option.


Should this be covered in the GCC 9 release notes at 
https://gcc.gnu.org/gcc-9/changes.html ?

(See https://gcc.gnu.org/about.html for how to go about web changes.)

Gerald

Patch

From 9878f38a3de6001e8876d21f03adbb7ebf551a79 Mon Sep 17 00:00:00 2001
From: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Mon, 26 Nov 2018 16:48:46 +0000
Subject: [PATCH] [Arm] Fix fpu configurations for Cortex-R7 and Cortex-R8

Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both have
SP only and SP + DP configurations.
---
 gcc/config/arm/arm-cpus.in | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index c71409e5dd9bcad525ed98cefd839bed0fd6f8ee..2fed508a46bc138caaac5d9905d8955e29eb7097 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -476,6 +476,8 @@  begin arch armv7-r
  optalias vfpv3xd fp.sp
  option fp add VFPv3 FP_DBL
  optalias vfpv3-d16 fp
+ option vfpv3xd-fp16 add VFPv3 fp16conv
+ option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv
  option idiv add adiv
  option nofp remove ALL_FP
  option noidiv remove adiv
@@ -1086,7 +1088,8 @@  end cpu cortex-r5
 begin cpu cortex-r7
  cname cortexr7
  tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
  vendor 41
@@ -1097,7 +1100,8 @@  begin cpu cortex-r8
  cname cortexr8
  tune for cortex-r7
  tune flags LDSCHED
- architecture armv7-r+idiv+fp
+ architecture armv7-r+idiv+vfpv3-d16-fp16
+ option nofp.dp remove FP_DBL
  option nofp remove ALL_FP
  costs cortex
  vendor 41
-- 
1.9.1