[10/10] Port testsuite to GCN

Message ID 2d4f15916d3fd76c3c125eca60a86f5be5b807c0.1542381960.git.ams@codesourcery.com
State New
Headers show
Series
  • AMD GCN Port v2
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Commit Message

Andrew Stubbs Nov. 16, 2018, 4:29 p.m.
This collection of miscellaneous patches configures the testsuite to run on AMD
GCN in a standalone (i.e. not offloading) configuration.  It assumes you have
your Dejagnu set up to run binaries via the gcn-run tool.

2018-11-16  Andrew Stubbs  <ams@codesourcery.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Tom de Vries  <tom@codesourcery.com>

	gcc/testsuite/
	* gcc.dg/20020312-2.c: Add amdgcn support.
	* gcc.dg/Wno-frame-address.c: Disable on amdgcn.
	* gcc.dg/builtin-apply2.c: Likewise.
	* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
	* gcc.dg/gimplefe-28.c: Force -ffast-math.
	* gcc.dg/intermod-1.c: Add -mlocal-symbol-id on amdgcn.
	* gcc.dg/memcmp-1.c: Increase timeout factor.
	* gcc.dg/pr59605-2.c: Addd -DMAX_COPY=1025 on amdgcn.
	* gcc.dg/sibcall-10.c: xfail on amdgcn.
	* gcc.dg/sibcall-9.c: Likewise.
	* gcc.dg/tree-ssa/gen-vect-11c.c: Likewise.
	* gcc.dg/tree-ssa/pr84512.c: Likewise.
	* gcc.dg/tree-ssa/loop-1.c: Adjust expectations for amdgcn.
	* gfortran.dg/bind_c_array_params_2.f90: Likewise.
	* gcc.dg/vect/tree-vect.h: Avoid signal on amdgcn.
	* lib/target-supports.exp (check_effective_target_trampolines):
	Configure amdgcn.
	(check_profiling_available): Likewise.
	(check_effective_target_global_constructor): Likewise.
	(check_effective_target_return_address): Likewise.
	(check_effective_target_fopenacc): Likewise.
	(check_effective_target_fopenmp): Likewise.
	(check_effective_target_vect_int): Likewise.
	(check_effective_target_vect_intfloat_cvt): Likewise.
	(check_effective_target_vect_uintfloat_cvt): Likewise.
	(check_effective_target_vect_floatint_cvt): Likewise.
	(check_effective_target_vect_floatuint_cvt): Likewise.
	(check_effective_target_vect_simd_clones): Likewise.
	(check_effective_target_vect_shift): Likewise.
	(check_effective_target_whole_vector_shift): Likewise.
	(check_effective_target_vect_bswap): Likewise.
	(check_effective_target_vect_shift_char): Likewise.
	(check_effective_target_vect_long): Likewise.
	(check_effective_target_vect_float): Likewise.
	(check_effective_target_vect_double): Likewise.
	(check_effective_target_vect_perm): Likewise.
	(check_effective_target_vect_perm_byte): Likewise.
	(check_effective_target_vect_perm_short): Likewise.
	(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
	(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
	(check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise.
	(check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise.
	(check_effective_target_vect_natural_alignment): Likewise.
	(check_effective_target_vect_fully_masked): Likewise.
	(check_effective_target_vect_element_align): Likewise.
	(check_effective_target_vect_masked_store): Likewise.
	(check_effective_target_vect_scatter_store): Likewise.
	(check_effective_target_vect_condition): Likewise.
	(check_effective_target_vect_cond_mixed): Likewise.
	(check_effective_target_vect_char_mult): Likewise.
	(check_effective_target_vect_short_mult): Likewise.
	(check_effective_target_vect_int_mult): Likewise.
	(check_effective_target_sqrt_insn): Likewise.
	(check_effective_target_vect_call_sqrtf): Likewise.
	(check_effective_target_vect_call_btrunc): Likewise.
	(check_effective_target_vect_call_btruncf): Likewise.
	(check_effective_target_vect_call_ceil): Likewise.
	(check_effective_target_vect_call_floorf): Likewise.
	(check_effective_target_lto): Likewise.
	(check_vect_support_and_set_flags): Likewise.
	(check_effective_target_vect_stridedN): Enable when fully masked is
	available.
---
 gcc/testsuite/gcc.dg/20020312-2.c                  |   2 +
 gcc/testsuite/gcc.dg/Wno-frame-address.c           |   2 +-
 gcc/testsuite/gcc.dg/builtin-apply2.c              |   2 +-
 gcc/testsuite/gcc.dg/gimplefe-28.c                 |   2 +-
 gcc/testsuite/gcc.dg/intermod-1.c                  |   1 +
 gcc/testsuite/gcc.dg/memcmp-1.c                    |   1 +
 gcc/testsuite/gcc.dg/pr59605-2.c                   |   2 +-
 gcc/testsuite/gcc.dg/sibcall-10.c                  |   2 +-
 gcc/testsuite/gcc.dg/sibcall-9.c                   |   2 +-
 .../gcc.dg/torture/stackalign/builtin-apply-2.c    |   2 +-
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c       |   2 +-
 gcc/testsuite/gcc.dg/tree-ssa/loop-1.c             |   6 +-
 gcc/testsuite/gcc.dg/tree-ssa/pr84512.c            |   2 +-
 gcc/testsuite/gcc.dg/vect/tree-vect.h              |   4 +
 .../gfortran.dg/bind_c_array_params_2.f90          |   3 +-
 gcc/testsuite/lib/target-supports.exp              | 129 +++++++++++++++------
 16 files changed, 115 insertions(+), 49 deletions(-)

Comments

Jeff Law Nov. 21, 2018, 1 a.m. | #1
On 11/16/18 9:29 AM, Andrew Stubbs wrote:
> This collection of miscellaneous patches configures the testsuite to run on AMD

> GCN in a standalone (i.e. not offloading) configuration.  It assumes you have

> your Dejagnu set up to run binaries via the gcn-run tool.

> 

> 2018-11-16  Andrew Stubbs  <ams@codesourcery.com>

> 	    Kwok Cheung Yeung  <kcy@codesourcery.com>

> 	    Julian Brown  <julian@codesourcery.com>

> 	    Tom de Vries  <tom@codesourcery.com>

> 

> 	gcc/testsuite/

> 	* gcc.dg/20020312-2.c: Add amdgcn support.

> 	* gcc.dg/Wno-frame-address.c: Disable on amdgcn.

> 	* gcc.dg/builtin-apply2.c: Likewise.

> 	* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.

> 	* gcc.dg/gimplefe-28.c: Force -ffast-math.

> 	* gcc.dg/intermod-1.c: Add -mlocal-symbol-id on amdgcn.

> 	* gcc.dg/memcmp-1.c: Increase timeout factor.

> 	* gcc.dg/pr59605-2.c: Addd -DMAX_COPY=1025 on amdgcn.

> 	* gcc.dg/sibcall-10.c: xfail on amdgcn.

> 	* gcc.dg/sibcall-9.c: Likewise.

> 	* gcc.dg/tree-ssa/gen-vect-11c.c: Likewise.

> 	* gcc.dg/tree-ssa/pr84512.c: Likewise.

> 	* gcc.dg/tree-ssa/loop-1.c: Adjust expectations for amdgcn.

> 	* gfortran.dg/bind_c_array_params_2.f90: Likewise.

> 	* gcc.dg/vect/tree-vect.h: Avoid signal on amdgcn.

> 	* lib/target-supports.exp (check_effective_target_trampolines):

> 	Configure amdgcn.

> 	(check_profiling_available): Likewise.

> 	(check_effective_target_global_constructor): Likewise.

> 	(check_effective_target_return_address): Likewise.

> 	(check_effective_target_fopenacc): Likewise.

> 	(check_effective_target_fopenmp): Likewise.

> 	(check_effective_target_vect_int): Likewise.

> 	(check_effective_target_vect_intfloat_cvt): Likewise.

> 	(check_effective_target_vect_uintfloat_cvt): Likewise.

> 	(check_effective_target_vect_floatint_cvt): Likewise.

> 	(check_effective_target_vect_floatuint_cvt): Likewise.

> 	(check_effective_target_vect_simd_clones): Likewise.

> 	(check_effective_target_vect_shift): Likewise.

> 	(check_effective_target_whole_vector_shift): Likewise.

> 	(check_effective_target_vect_bswap): Likewise.

> 	(check_effective_target_vect_shift_char): Likewise.

> 	(check_effective_target_vect_long): Likewise.

> 	(check_effective_target_vect_float): Likewise.

> 	(check_effective_target_vect_double): Likewise.

> 	(check_effective_target_vect_perm): Likewise.

> 	(check_effective_target_vect_perm_byte): Likewise.

> 	(check_effective_target_vect_perm_short): Likewise.

> 	(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.

> 	(check_effective_target_vect_widen_mult_hi_to_si): Likewise.

> 	(check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise.

> 	(check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise.

> 	(check_effective_target_vect_natural_alignment): Likewise.

> 	(check_effective_target_vect_fully_masked): Likewise.

> 	(check_effective_target_vect_element_align): Likewise.

> 	(check_effective_target_vect_masked_store): Likewise.

> 	(check_effective_target_vect_scatter_store): Likewise.

> 	(check_effective_target_vect_condition): Likewise.

> 	(check_effective_target_vect_cond_mixed): Likewise.

> 	(check_effective_target_vect_char_mult): Likewise.

> 	(check_effective_target_vect_short_mult): Likewise.

> 	(check_effective_target_vect_int_mult): Likewise.

> 	(check_effective_target_sqrt_insn): Likewise.

> 	(check_effective_target_vect_call_sqrtf): Likewise.

> 	(check_effective_target_vect_call_btrunc): Likewise.

> 	(check_effective_target_vect_call_btruncf): Likewise.

> 	(check_effective_target_vect_call_ceil): Likewise.

> 	(check_effective_target_vect_call_floorf): Likewise.

> 	(check_effective_target_lto): Likewise.

> 	(check_vect_support_and_set_flags): Likewise.

> 	(check_effective_target_vect_stridedN): Enable when fully masked is

> 	available.

> ---



>  

> diff --git a/gcc/testsuite/gcc.dg/gimplefe-28.c b/gcc/testsuite/gcc.dg/gimplefe-28.c

> index 467172d..57b6e1f 100644

> --- a/gcc/testsuite/gcc.dg/gimplefe-28.c

> +++ b/gcc/testsuite/gcc.dg/gimplefe-28.c

> @@ -1,5 +1,5 @@

>  /* { dg-do compile { target sqrt_insn } } */

> -/* { dg-options "-fgimple -O2" } */

> +/* { dg-options "-fgimple -O2 -ffast-math" } */

So why does the GCN need fast-math here?  I'm not aware of any other
target  that needs that kind of handling to make this test work.


> diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h

> index 69c93ac..2ddfa5e 100644

> --- a/gcc/testsuite/gcc.dg/vect/tree-vect.h

> +++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h

> @@ -1,5 +1,9 @@

>  /* Check if system supports SIMD */

> +#ifdef __AMDGCN__

> +#define signal(A,B)

> +#else

>  #include <signal.h>

> +#endif

Presumably you don't have signals.  Though one could make an argument
that this really shouldn't be exposed in the testsuite.  It kindof sets
up a need to have this kind of ifdef in any test that wants to include
signal.h.  Is there no way to create a dummy signal.h with the magic
#define in whatever fake library you're using?


The rest seems pretty reasonable.

jeff
Mike Stump Nov. 26, 2018, 8:04 p.m. | #2
On Nov 20, 2018, at 5:00 PM, Jeff Law <law@redhat.com> wrote:
> 

> On 11/16/18 9:29 AM, Andrew Stubbs wrote:

>> This collection of miscellaneous patches configures the testsuite to run on AMD

>> GCN in a standalone (i.e. not offloading) configuration.  It assumes you have

>> your Dejagnu set up to run binaries via the gcn-run tool.

>> 

>> 2018-11-16  Andrew Stubbs  <ams@codesourcery.com>

>> 	    Kwok Cheung Yeung  <kcy@codesourcery.com>

>> 	    Julian Brown  <julian@codesourcery.com>

>> 	    Tom de Vries  <tom@codesourcery.com>

>> 

>> 	gcc/testsuite/

>> 	* gcc.dg/20020312-2.c: Add amdgcn support.

>> 	* gcc.dg/Wno-frame-address.c: Disable on amdgcn.

>> 	* gcc.dg/builtin-apply2.c: Likewise.

>> 	* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.

>> 	* gcc.dg/gimplefe-28.c: Force -ffast-math.

>> 	* gcc.dg/intermod-1.c: Add -mlocal-symbol-id on amdgcn.

>> 	* gcc.dg/memcmp-1.c: Increase timeout factor.

>> 	* gcc.dg/pr59605-2.c: Addd -DMAX_COPY=1025 on amdgcn.

>> 	* gcc.dg/sibcall-10.c: xfail on amdgcn.

>> 	* gcc.dg/sibcall-9.c: Likewise.

>> 	* gcc.dg/tree-ssa/gen-vect-11c.c: Likewise.

>> 	* gcc.dg/tree-ssa/pr84512.c: Likewise.

>> 	* gcc.dg/tree-ssa/loop-1.c: Adjust expectations for amdgcn.

>> 	* gfortran.dg/bind_c_array_params_2.f90: Likewise.

>> 	* gcc.dg/vect/tree-vect.h: Avoid signal on amdgcn.

>> 	* lib/target-supports.exp (check_effective_target_trampolines):

>> 	Configure amdgcn.

>> 	(check_profiling_available): Likewise.

>> 	(check_effective_target_global_constructor): Likewise.

>> 	(check_effective_target_return_address): Likewise.

>> 	(check_effective_target_fopenacc): Likewise.

>> 	(check_effective_target_fopenmp): Likewise.

>> 	(check_effective_target_vect_int): Likewise.

>> 	(check_effective_target_vect_intfloat_cvt): Likewise.

>> 	(check_effective_target_vect_uintfloat_cvt): Likewise.

>> 	(check_effective_target_vect_floatint_cvt): Likewise.

>> 	(check_effective_target_vect_floatuint_cvt): Likewise.

>> 	(check_effective_target_vect_simd_clones): Likewise.

>> 	(check_effective_target_vect_shift): Likewise.

>> 	(check_effective_target_whole_vector_shift): Likewise.

>> 	(check_effective_target_vect_bswap): Likewise.

>> 	(check_effective_target_vect_shift_char): Likewise.

>> 	(check_effective_target_vect_long): Likewise.

>> 	(check_effective_target_vect_float): Likewise.

>> 	(check_effective_target_vect_double): Likewise.

>> 	(check_effective_target_vect_perm): Likewise.

>> 	(check_effective_target_vect_perm_byte): Likewise.

>> 	(check_effective_target_vect_perm_short): Likewise.

>> 	(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.

>> 	(check_effective_target_vect_widen_mult_hi_to_si): Likewise.

>> 	(check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise.

>> 	(check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise.

>> 	(check_effective_target_vect_natural_alignment): Likewise.

>> 	(check_effective_target_vect_fully_masked): Likewise.

>> 	(check_effective_target_vect_element_align): Likewise.

>> 	(check_effective_target_vect_masked_store): Likewise.

>> 	(check_effective_target_vect_scatter_store): Likewise.

>> 	(check_effective_target_vect_condition): Likewise.

>> 	(check_effective_target_vect_cond_mixed): Likewise.

>> 	(check_effective_target_vect_char_mult): Likewise.

>> 	(check_effective_target_vect_short_mult): Likewise.

>> 	(check_effective_target_vect_int_mult): Likewise.

>> 	(check_effective_target_sqrt_insn): Likewise.

>> 	(check_effective_target_vect_call_sqrtf): Likewise.

>> 	(check_effective_target_vect_call_btrunc): Likewise.

>> 	(check_effective_target_vect_call_btruncf): Likewise.

>> 	(check_effective_target_vect_call_ceil): Likewise.

>> 	(check_effective_target_vect_call_floorf): Likewise.

>> 	(check_effective_target_lto): Likewise.

>> 	(check_vect_support_and_set_flags): Likewise.

>> 	(check_effective_target_vect_stridedN): Enable when fully masked is

>> 	available.

>> ---

> 

> 

>> 

>> diff --git a/gcc/testsuite/gcc.dg/gimplefe-28.c b/gcc/testsuite/gcc.dg/gimplefe-28.c

>> index 467172d..57b6e1f 100644

>> --- a/gcc/testsuite/gcc.dg/gimplefe-28.c

>> +++ b/gcc/testsuite/gcc.dg/gimplefe-28.c

>> @@ -1,5 +1,5 @@

>> /* { dg-do compile { target sqrt_insn } } */

>> -/* { dg-options "-fgimple -O2" } */

>> +/* { dg-options "-fgimple -O2 -ffast-math" } */

> So why does the GCN need fast-math here?  I'm not aware of any other

> target  that needs that kind of handling to make this test work.

> 

> 

>> diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h

>> index 69c93ac..2ddfa5e 100644

>> --- a/gcc/testsuite/gcc.dg/vect/tree-vect.h

>> +++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h

>> @@ -1,5 +1,9 @@

>> /* Check if system supports SIMD */

>> +#ifdef __AMDGCN__

>> +#define signal(A,B)

>> +#else

>> #include <signal.h>

>> +#endif

> Presumably you don't have signals.  Though one could make an argument

> that this really shouldn't be exposed in the testsuite.  It kindof sets

> up a need to have this kind of ifdef in any test that wants to include

> signal.h.  Is there no way to create a dummy signal.h with the magic

> #define in whatever fake library you're using?

> 

> 

> The rest seems pretty reasonable.


Since Jeff didn't explicitly say Ok to the rest, let me, Ok for the rest.

I'll Ok the signal one, if you prefer it over a dummy signal routine.  Though, would be nice for you to add signal if possible/reasonable.
Mike Stump Nov. 26, 2018, 9:13 p.m. | #3
On Nov 26, 2018, at 12:04 PM, Mike Stump <mikestump@comcast.net> wrote:
> 

> I'll Ok the signal one, if you prefer it over a dummy signal routine.  Though, would be nice for you to add signal if possible/reasonable.


Oh, and my long term thinking on signal is that logically, it's fine to have:

#if __has_include("signal.h")
  signal(...);
#endif

and once we have a way to do that, then the processor specific test goes away.  Over time, it does seem that we add more introspection capabilities to the compiler, and introspection on what headers are there, is pretty basic, so I can see that one day, I expect we'll get support for it.

Indeed, I was looking at the laundry list of changes a port did recently (effective target changes), and was wondering if all these would be better served by the compiler setting up those values for introspection, and the testsuite using those values from introspection.

Hum, [ testing ] we already have it, welcome to the future I guess.  Could you please use the above form instead?  I can't think of any down side to doing it this way.
Andrew Stubbs Nov. 27, 2018, 9:26 a.m. | #4
On 26/11/2018 21:13, Mike Stump wrote:
> On Nov 26, 2018, at 12:04 PM, Mike Stump <mikestump@comcast.net> wrote:

>>

>> I'll Ok the signal one, if you prefer it over a dummy signal routine.  Though, would be nice for you to add signal if possible/reasonable.

> 

> Oh, and my long term thinking on signal is that logically, it's fine to have:

> 

> #if __has_include("signal.h")

>    signal(...);

> #endif

> 

> and once we have a way to do that, then the processor specific test goes away.  Over time, it does seem that we add more introspection capabilities to the compiler, and introspection on what headers are there, is pretty basic, so I can see that one day, I expect we'll get support for it.

> 

> Indeed, I was looking at the laundry list of changes a port did recently (effective target changes), and was wondering if all these would be better served by the compiler setting up those values for introspection, and the testsuite using those values from introspection.

> 

> Hum, [ testing ] we already have it, welcome to the future I guess.  Could you please use the above form instead?  I can't think of any down side to doing it this way.


Thanks, I've been meaning to test why we have that, but I'm working on 
addressing Jeff's review of my other patch right now.

I'll do it as you suggest, if I don't find a better way.

Andrew
Andrew Stubbs Dec. 6, 2018, 3:26 p.m. | #5
I finally got back to investigating this ....

On 21/11/2018 01:00, Jeff Law wrote:
>> --- a/gcc/testsuite/gcc.dg/gimplefe-28.c

>> +++ b/gcc/testsuite/gcc.dg/gimplefe-28.c

>> @@ -1,5 +1,5 @@

>>   /* { dg-do compile { target sqrt_insn } } */

>> -/* { dg-options "-fgimple -O2" } */

>> +/* { dg-options "-fgimple -O2 -ffast-math" } */

> So why does the GCN need fast-math here?  I'm not aware of any other

> target  that needs that kind of handling to make this test work.


It needs it because the sqrt instruction is only enabled when 
flag_unsafe_math_optimizations is set. This seems appropriate given the 
approximate nature of the machine instruction.

This test uses gimple directly and so bypasses the usual optab checks 
that would normally select a library function instead, which results in 
an ICE.

It seems like a safe change to make, since most targets will have more 
patterns enabled, not fewer, in this mode.

The test will continue to fail on any target that does not have a sqrt 
instruction at all.

Andrew
Andrew Stubbs Dec. 6, 2018, 4:10 p.m. | #6
On 26/11/2018 21:13, Mike Stump wrote:
> On Nov 26, 2018, at 12:04 PM, Mike Stump <mikestump@comcast.net> wrote:

>>

>> I'll Ok the signal one, if you prefer it over a dummy signal routine.  Though, would be nice for you to add signal if possible/reasonable.

> 

> Oh, and my long term thinking on signal is that logically, it's fine to have:

> 

> #if __has_include("signal.h")

>    signal(...);

> #endif


This doesn't work here because we have signal.h (and indeed "signal").

The problem is that the function doesn't work (actually, it doesn't 
link, because "kill" is missing).

I've solved the problem by adding a machine-specific stub function in 
Newlib, so we can drop this portion of the patch from the testsuite now.

Andrew
Richard Sandiford Dec. 8, 2018, 12:05 p.m. | #7
Andrew Stubbs <ams@codesourcery.com> writes:
> I finally got back to investigating this ....

>

> On 21/11/2018 01:00, Jeff Law wrote:

>>> --- a/gcc/testsuite/gcc.dg/gimplefe-28.c

>>> +++ b/gcc/testsuite/gcc.dg/gimplefe-28.c

>>> @@ -1,5 +1,5 @@

>>>   /* { dg-do compile { target sqrt_insn } } */

>>> -/* { dg-options "-fgimple -O2" } */

>>> +/* { dg-options "-fgimple -O2 -ffast-math" } */

>> So why does the GCN need fast-math here?  I'm not aware of any other

>> target  that needs that kind of handling to make this test work.

>

> It needs it because the sqrt instruction is only enabled when 

> flag_unsafe_math_optimizations is set. This seems appropriate given the 

> approximate nature of the machine instruction.

>

> This test uses gimple directly and so bypasses the usual optab checks 

> that would normally select a library function instead, which results in 

> an ICE.

>

> It seems like a safe change to make, since most targets will have more 

> patterns enabled, not fewer, in this mode.

>

> The test will continue to fail on any target that does not have a sqrt 

> instruction at all.


But then I think we'll end up doing this for other (future) tests gated
on sqrt_insn, which would reduce the sqrt coverage for targets that don't
need -ffast-math.

I think it'd be better to define add_options_for_sqrt_insn, returning
"-ffast-math" for GCN and "" for everything else.  Then the test can use:

/* { dg-add-options sqrt_insn } */

after the dg-options line.

Thanks,
Richard

Patch

diff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c
index e72a5b2..c584d35 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -119,6 +119,8 @@  extern void abort (void);
 # endif
 #elif defined (__or1k__)
 /* No pic register.  */
+#elif defined (__AMDGCN__)
+/* No pic register.  */
 #else
 # error "Modify the test for your target."
 #endif
diff --git a/gcc/testsuite/gcc.dg/Wno-frame-address.c b/gcc/testsuite/gcc.dg/Wno-frame-address.c
index 9fe4d07..5e3ef7a 100644
--- a/gcc/testsuite/gcc.dg/Wno-frame-address.c
+++ b/gcc/testsuite/gcc.dg/Wno-frame-address.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-skip-if "Cannot access arbitrary stack frames" { arm*-*-* avr-*-* hppa*-*-* ia64-*-* visium-*-* csky-*-* } } */
+/* { dg-skip-if "Cannot access arbitrary stack frames" { arm*-*-* amdgpu-*-* avr-*-* hppa*-*-* ia64-*-* visium-*-* csky-*-* } } */
 /* { dg-options "-Werror" } */
 /* { dg-additional-options "-mbackchain" { target { s390*-*-* } } } */
 
diff --git a/gcc/testsuite/gcc.dg/builtin-apply2.c b/gcc/testsuite/gcc.dg/builtin-apply2.c
index dd52197..45b821a 100644
--- a/gcc/testsuite/gcc.dg/builtin-apply2.c
+++ b/gcc/testsuite/gcc.dg/builtin-apply2.c
@@ -1,6 +1,6 @@ 
 /* { dg-do run } */
 /* { dg-require-effective-target untyped_assembly } */
-/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-*" } } */
+/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-* amdgcn-*-*" } } */
 /* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-* or1k*-*-*" } } */
 /* { dg-skip-if "Variadic funcs use Base AAPCS.  Normal funcs use VFP variant." { arm*-*-* && arm_hf_eabi } } */
 
diff --git a/gcc/testsuite/gcc.dg/gimplefe-28.c b/gcc/testsuite/gcc.dg/gimplefe-28.c
index 467172d..57b6e1f 100644
--- a/gcc/testsuite/gcc.dg/gimplefe-28.c
+++ b/gcc/testsuite/gcc.dg/gimplefe-28.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile { target sqrt_insn } } */
-/* { dg-options "-fgimple -O2" } */
+/* { dg-options "-fgimple -O2 -ffast-math" } */
 
 double __GIMPLE
 f1 (double x)
diff --git a/gcc/testsuite/gcc.dg/intermod-1.c b/gcc/testsuite/gcc.dg/intermod-1.c
index 9f8d19d..44a8ce0 100644
--- a/gcc/testsuite/gcc.dg/intermod-1.c
+++ b/gcc/testsuite/gcc.dg/intermod-1.c
@@ -1,4 +1,5 @@ 
 /* { dg-do compile } */
+/* { dg-additional-options "-mlocal-symbol-id=" { target amdgcn-*-* } } */
 /* { dg-final { scan-assembler-not {foo[1-9]\.[0-9]} } } */
 
 /* Check that we don't get .0 suffixes on static variables when not using
diff --git a/gcc/testsuite/gcc.dg/memcmp-1.c b/gcc/testsuite/gcc.dg/memcmp-1.c
index 619cf9b..ea837ca 100644
--- a/gcc/testsuite/gcc.dg/memcmp-1.c
+++ b/gcc/testsuite/gcc.dg/memcmp-1.c
@@ -2,6 +2,7 @@ 
 /* { dg-do run } */
 /* { dg-options "-O2" } */
 /* { dg-require-effective-target ptr32plus } */
+/* { dg-timeout-factor 2 } */
 
 #include <stdio.h>
 #include <stdlib.h>
diff --git a/gcc/testsuite/gcc.dg/pr59605-2.c b/gcc/testsuite/gcc.dg/pr59605-2.c
index 6d6ff23..9575481 100644
--- a/gcc/testsuite/gcc.dg/pr59605-2.c
+++ b/gcc/testsuite/gcc.dg/pr59605-2.c
@@ -1,6 +1,6 @@ 
 /* { dg-do run } */
 /* { dg-options "-O2" } */
-/* { dg-additional-options "-DMAX_COPY=1025" { target { { simulator } || { nvptx-*-* } } } } */
+/* { dg-additional-options "-DMAX_COPY=1025" { target { { simulator } || { nvptx-*-* amdgcn*-*-* } } } } */
 /* { dg-additional-options "-minline-stringops-dynamically" { target { i?86-*-* x86_64-*-* } } } */
 
 #include "pr59605.c"
diff --git a/gcc/testsuite/gcc.dg/sibcall-10.c b/gcc/testsuite/gcc.dg/sibcall-10.c
index 4acca50..3d58036 100644
--- a/gcc/testsuite/gcc.dg/sibcall-10.c
+++ b/gcc/testsuite/gcc.dg/sibcall-10.c
@@ -5,7 +5,7 @@ 
    Copyright (C) 2002 Free Software Foundation Inc.
    Contributed by Hans-Peter Nilsson  <hp@bitrange.com>  */
 
-/* { dg-do run { xfail { { cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
+/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* -msave-restore disables sibcall patterns.  */
diff --git a/gcc/testsuite/gcc.dg/sibcall-9.c b/gcc/testsuite/gcc.dg/sibcall-9.c
index 32b2e1d..6df671d 100644
--- a/gcc/testsuite/gcc.dg/sibcall-9.c
+++ b/gcc/testsuite/gcc.dg/sibcall-9.c
@@ -5,7 +5,7 @@ 
    Copyright (C) 2002 Free Software Foundation Inc.
    Contributed by Hans-Peter Nilsson  <hp@bitrange.com>  */
 
-/* { dg-do run { xfail { { cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
+/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* -msave-restore disables sibcall patterns.  */
diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
index dde2600..7e4ee9c 100644
--- a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
+++ b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
@@ -9,7 +9,7 @@ 
 /* arm_hf_eabi: Variadic funcs use Base AAPCS.  Normal funcs use VFP variant.
    avr: Variadic funcs don't pass arguments in registers, while normal funcs
         do.  */
-/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* or1k*-*-* } } } */
+/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* or1k*-*-* amdgcn-*-* } } } */
 /* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } { v850*-*-* } } */
 /* { dg-require-effective-target untyped_assembly } */
    
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
index 236d3a5..22ff44c 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
@@ -39,4 +39,4 @@  int main ()
 }
 
 
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail amdgcn*-*-* } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
index 1862750..f422f39 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
@@ -45,8 +45,10 @@  int xxx(void)
    relaxation.  */
 /* CRIS keeps the address in a register.  */
 /* m68k sometimes puts the address in a register, depending on CPU and PIC.  */
+/* AMD GCN loads symbol addresses as hi/lo pairs, and then reuses that for
+   each jump.  */
 
-/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* } } } */
+/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* amdgcn*-*-* } } } */
 /* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
 /* { dg-final { scan-assembler-times "= foo"  5 { target ia64*-*-* } } } */
 /* { dg-final { scan-assembler-times "call\[ \t\]*_foo" 5 { target i?86-*-mingw* i?86-*-cygwin* } } } */
@@ -56,3 +58,5 @@  int xxx(void)
 /* { dg-final { scan-assembler-times "\[jb\]sr" 5 { target fido-*-* m68k-*-* } } } */
 /* { dg-final { scan-assembler-times "bra *tr,r\[1-9\]*,r21" 5 { target visium-*-* } } } */
 /* { dg-final { scan-assembler-times "(?n)\[ \t\]call\[ \t\].*\[ \t\]foo," 5 { target nvptx*-*-* } } } */
+/* { dg-final { scan-assembler-times "add_u32\t\[sv\]\[0-9\]*, \[sv\]\[0-9\]*, foo@rel32@lo" 1 { target { amdgcn*-*-* } } } } */
+/* { dg-final { scan-assembler-times "s_swappc_b64" 5 { target { amdgcn*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr84512.c b/gcc/testsuite/gcc.dg/tree-ssa/pr84512.c
index 056d1c4..3975757 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr84512.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr84512.c
@@ -13,4 +13,4 @@  int foo()
 }
 
 /* Listed targets xfailed due to PR84958.  */
-/* { dg-final { scan-tree-dump "return 285;" "optimized" { xfail { { alpha*-*-* nvptx*-*-* } || { sparc*-*-* && lp64 } } } } } */
+/* { dg-final { scan-tree-dump "return 285;" "optimized" { xfail { { alpha*-*-* amdgcn*-*-* nvptx*-*-* } || { sparc*-*-* && lp64 } } } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h
index 69c93ac..2ddfa5e 100644
--- a/gcc/testsuite/gcc.dg/vect/tree-vect.h
+++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h
@@ -1,5 +1,9 @@ 
 /* Check if system supports SIMD */
+#ifdef __AMDGCN__
+#define signal(A,B)
+#else
 #include <signal.h>
+#endif
 
 #if defined(__i386__) || defined(__x86_64__)
 # include "cpuid.h"
diff --git a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
index 25f5dda..34ed055 100644
--- a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
+++ b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
@@ -16,8 +16,9 @@  integer :: aa(4,4)
 call test(aa)
 end
 
-! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* } } } } }
+! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* } } } } }
 ! { dg-final { scan-assembler-times "myBindC,%r2" 1 { target { hppa*-*-* } } } }
 ! { dg-final { scan-assembler-times "call\tmyBindC" 1 { target { *-*-cygwin* } } } }
 ! { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,myBindC" 1 { target { s390*-*-* } } } }
+! { dg-final { scan-assembler-times "add_u32\t\[sv\]\[0-9\]*, \[sv\]\[0-9\]*, myBindC@rel32@lo" 1 { target { amdgcn*-*-* } } } }
 ! { dg-final { scan-tree-dump-times "test \\\(&parm\\." 1 "original" } }
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f15e679..0956857 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -651,6 +651,7 @@  proc check_profiling_available { test_what } {
 	# missing other needed machinery.
 	if {[istarget aarch64*-*-elf]
 	     || [istarget am3*-*-linux*]
+	     || [istarget amdgcn-*-*]
 	     || [istarget arm*-*-eabi*]
 	     || [istarget arm*-*-elf]
 	     || [istarget arm*-*-symbianelf*]
@@ -776,6 +777,9 @@  proc check_effective_target_global_constructor {} {
     if { [istarget nvptx-*-*] } {
 	return 0
     }
+    if { [istarget amdgcn-*-*] } {
+	return 0
+    }
     return 1
 }
 
@@ -796,6 +800,10 @@  proc check_effective_target_return_address {} {
     if { [istarget nvptx-*-*] } {
 	return 0
     }
+    # It could be supported on amdgcn, but isn't yet.
+    if { [istarget amdgcn*-*-*] } {
+	return 0
+    }
     return 1
 }
 
@@ -937,9 +945,10 @@  proc check_effective_target_fgraphite {} {
 # code, 0 otherwise.
 
 proc check_effective_target_fopenacc {} {
-    # nvptx can be built with the device-side bits of openacc, but it
+    # nvptx/amdgcn can be built with the device-side bits of openacc, but it
     # does not make sense to test it as an openacc host.
     if [istarget nvptx-*-*] { return 0 }
+    if [istarget amdgcn-*-*] { return 0 }
 
     return [check_no_compiler_messages fopenacc object {
 	void foo (void) { }
@@ -950,9 +959,10 @@  proc check_effective_target_fopenacc {} {
 # code, 0 otherwise.
 
 proc check_effective_target_fopenmp {} {
-    # nvptx can be built with the device-side bits of libgomp, but it
+    # nvptx/amdgcn can be built with the device-side bits of libgomp, but it
     # does not make sense to test it as an openmp host.
     if [istarget nvptx-*-*] { return 0 }
+    if [istarget amdgcn-*-*] { return 0 }
 
     return [check_no_compiler_messages fopenmp object {
 	void foo (void) { }
@@ -3079,6 +3089,7 @@  proc check_effective_target_vect_int { } {
          [istarget i?86-*-*] || [istarget x86_64-*-*]
          || ([istarget powerpc*-*-*]
 	     && ![istarget powerpc-*-linux*paired*])
+	 || [istarget amdgcn-*-*]
 	 || [istarget spu-*-*]
 	 || [istarget sparc*-*-*]
 	 || [istarget alpha*-*-*]
@@ -3103,7 +3114,8 @@  proc check_effective_target_vect_intfloat_cvt { } {
 		 && ![istarget powerpc-*-linux*paired*])
 	     || [is-effective-target arm_neon]
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports signed double->int conversion
@@ -3167,7 +3179,8 @@  proc check_effective_target_vect_uintfloat_cvt { } {
 	     || [istarget aarch64*-*-*]
 	     || [is-effective-target arm_neon]
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 
@@ -3181,7 +3194,8 @@  proc check_effective_target_vect_floatint_cvt { } {
 		 && ![istarget powerpc-*-linux*paired*])
 	     || [is-effective-target arm_neon]
 	     || ([istarget mips*-*-*]
-		 && [et-is-effective-target mips_msa]) }}]
+		 && [et-is-effective-target mips_msa])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports unsigned float->int conversion
@@ -3193,7 +3207,8 @@  proc check_effective_target_vect_floatuint_cvt { } {
 	      && ![istarget powerpc-*-linux*paired*])
 	    || [is-effective-target arm_neon]
 	    || ([istarget mips*-*-*]
-		&& [et-is-effective-target mips_msa]) }}]
+		&& [et-is-effective-target mips_msa])
+	    || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if peeling for alignment might be profitable on the target
@@ -3217,7 +3232,8 @@  proc check_effective_target_vect_simd_clones { } {
     # be able to assemble avx512f.
     return [check_cached_effective_target_indexed vect_simd_clones {
       expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
-	      && [check_effective_target_avx512f]) }}]
+	      && [check_effective_target_avx512f])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if this is a AArch64 target supporting big endian
@@ -5327,7 +5343,8 @@  proc check_effective_target_vect_shift { } {
 		 && ([et-is-effective-target mips_msa]
 		     || [et-is-effective-target mips_loongson_mmi]))
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports hardware vector shift by register operation.
@@ -5349,7 +5366,8 @@  proc check_effective_target_whole_vector_shift { } {
 	 || ([istarget mips*-*-*]
 	     && [et-is-effective-target mips_loongson_mmi])
 	 || ([istarget s390*-*-*]
-	     && [check_effective_target_s390_vx]) } {
+	     && [check_effective_target_s390_vx])
+	 || [istarget amdgcn-*-*] } {
 	set answer 1
     } else {
 	set answer 0
@@ -5363,7 +5381,9 @@  proc check_effective_target_whole_vector_shift { } {
 
 proc check_effective_target_vect_bswap { } {
     return [check_cached_effective_target_indexed vect_bswap {
-      expr { [istarget aarch64*-*-*] || [is-effective-target arm_neon] }}]
+      expr { [istarget aarch64*-*-*]
+	     || [is-effective-target arm_neon]
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports hardware vector shift operation for char.
@@ -5376,7 +5396,8 @@  proc check_effective_target_vect_shift_char { } {
 	     || ([istarget mips*-*-*]
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports hardware vectors of long, 0 otherwise.
@@ -5394,7 +5415,8 @@  proc check_effective_target_vect_long { } {
 	 || ([istarget mips*-*-*]
 	      && [et-is-effective-target mips_msa])
 	 || ([istarget s390*-*-*]
-	     && [check_effective_target_s390_vx]) } {
+	     && [check_effective_target_s390_vx])
+	 || [istarget amdgcn-*-*] } {
 	set answer 1
     } else {
 	set answer 0
@@ -5422,7 +5444,8 @@  proc check_effective_target_vect_float { } {
 		 && [et-is-effective-target mips_msa])
 	     || [is-effective-target arm_neon]
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vxe]) }}]
+		 && [check_effective_target_s390_vxe])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports hardware vectors of float without
@@ -5451,7 +5474,8 @@  proc check_effective_target_vect_double { } {
 	     || ([istarget mips*-*-*]
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx])} }]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*]} }]
 }
 
 # Return 1 if the target supports conditional addition, subtraction,
@@ -5526,7 +5550,8 @@  proc check_effective_target_vect_perm { } {
 		 && ([et-is-effective-target mpaired_single]
 		     || [et-is-effective-target mips_msa]))
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if, for some VF:
@@ -5619,7 +5644,8 @@  proc check_effective_target_vect_perm_byte { } {
 	     || ([istarget mips-*.*]
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports SLP permutation of 3 vectors when each
@@ -5648,7 +5674,8 @@  proc check_effective_target_vect_perm_short { } {
 	     || ([istarget mips*-*-*]
 		  && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports SLP permutation of 3 vectors when each
@@ -5739,7 +5766,8 @@  proc check_effective_target_vect_widen_mult_qi_to_hi { } {
 		      && ![check_effective_target_aarch64_sve])
 		  || [is-effective-target arm_neon]
 		  || ([istarget s390*-*-*]
-		      && [check_effective_target_s390_vx])) }}]
+		      && [check_effective_target_s390_vx])) 
+	      || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -5763,7 +5791,8 @@  proc check_effective_target_vect_widen_mult_hi_to_si { } {
 		 || [istarget i?86-*-*] || [istarget x86_64-*-*]
 		 || [is-effective-target arm_neon]
 		 || ([istarget s390*-*-*]
-		     && [check_effective_target_s390_vx])) }}]
+		     && [check_effective_target_s390_vx]))
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -5777,7 +5806,8 @@  proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
              || ([is-effective-target arm_neon]
 		 && [check_effective_target_arm_little_endian])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -5794,7 +5824,8 @@  proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
 	     || ([is-effective-target arm_neon]
 		 && [check_effective_target_arm_little_endian])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -6035,7 +6066,8 @@  proc check_effective_target_vect_natural_alignment { } {
     set et_vect_natural_alignment 1
     if { [check_effective_target_arm_eabi]
 	 || [istarget nvptx-*-*]
-	 || [istarget s390*-*-*] } {
+	 || [istarget s390*-*-*]
+	 || [istarget amdgcn-*-*] } {
 	set et_vect_natural_alignment 0
     }
     verbose "check_effective_target_vect_natural_alignment:\
@@ -6046,7 +6078,8 @@  proc check_effective_target_vect_natural_alignment { } {
 # Return true if fully-masked loops are supported.
 
 proc check_effective_target_vect_fully_masked { } {
-    return [check_effective_target_aarch64_sve]
+    return [expr { [check_effective_target_aarch64_sve]
+	           || [istarget amdgcn*-*-*] }]
 }
 
 # Return 1 if the target doesn't prefer any alignment beyond element
@@ -6098,7 +6131,8 @@  proc check_effective_target_vect_element_align { } {
     return [check_cached_effective_target_indexed vect_element_align {
       expr { ([istarget arm*-*-*]
 	      && ![check_effective_target_arm_vect_no_misalign])
-	     || [check_effective_target_vect_hw_misalign] }}]
+	     || [check_effective_target_vect_hw_misalign]
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if we expect to see unaligned accesses in at least some
@@ -6123,13 +6157,15 @@  proc check_effective_target_vect_load_lanes { } {
 # Return 1 if the target supports vector masked stores.
 
 proc check_effective_target_vect_masked_store { } {
-    return [check_effective_target_aarch64_sve]
+    return [expr { [check_effective_target_aarch64_sve]
+		   || [istarget amdgcn*-*-*] }]
 }
 
 # Return 1 if the target supports vector scatter stores.
 
 proc check_effective_target_vect_scatter_store { } {
-    return [check_effective_target_aarch64_sve]
+    return [expr { [check_effective_target_aarch64_sve]
+		   || [istarget amdgcn*-*-*] }]
 }
 
 # Return 1 if the target supports vector conditional operations, 0 otherwise.
@@ -6146,7 +6182,8 @@  proc check_effective_target_vect_condition { } {
 	     || ([istarget arm*-*-*]
 		 && [check_effective_target_arm_neon_ok])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector conditional operations where
@@ -6160,7 +6197,8 @@  proc check_effective_target_vect_cond_mixed { } {
 	     || ([istarget mips*-*-*]
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector char multiplication, 0 otherwise.
@@ -6175,7 +6213,8 @@  proc check_effective_target_vect_char_mult { } {
 	     || ([istarget mips*-*-*]
 		 && [et-is-effective-target mips_msa])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector short multiplication, 0 otherwise.
@@ -6192,7 +6231,8 @@  proc check_effective_target_vect_short_mult { } {
 		 && ([et-is-effective-target mips_msa]
 		     || [et-is-effective-target mips_loongson_mmi]))
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector int multiplication, 0 otherwise.
@@ -6208,7 +6248,8 @@  proc check_effective_target_vect_int_mult { } {
 		 && [et-is-effective-target mips_msa])
 	     || [check_effective_target_arm32]
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports 64 bit hardware vector
@@ -6283,6 +6324,9 @@  foreach N {2 3 4 8} {
 		      || [istarget aarch64*-*-*]) && N >= 2 && N <= 4 } {
 		    return 1
 		}
+		if [check_effective_target_vect_fully_masked] {
+		    return 1
+		}
 		return 0
 	    }]
 	}
@@ -6350,7 +6394,8 @@  proc check_effective_target_sqrt_insn { } {
 	     || [istarget aarch64*-*-*]
 	     || ([istarget arm*-*-*] && [check_effective_target_arm_vfp_ok])
 	     || ([istarget s390*-*-*]
-		 && [check_effective_target_s390_vx]) }}]
+		 && [check_effective_target_s390_vx])
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector sqrtf calls.
@@ -6369,7 +6414,8 @@  proc check_effective_target_vect_call_sqrtf { } {
 proc check_effective_target_vect_call_lrint { } {
     set et_vect_call_lrint 0
     if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
-	  && [check_effective_target_ilp32]) } {
+	  && [check_effective_target_ilp32])
+	 || [istarget amdgcn-*-*] } {
 	set et_vect_call_lrint 1
     }
 
@@ -6381,21 +6427,24 @@  proc check_effective_target_vect_call_lrint { } {
 
 proc check_effective_target_vect_call_btrunc { } {
     return [check_cached_effective_target_indexed vect_call_btrunc {
-      expr { [istarget aarch64*-*-*] }}]
+      expr { [istarget aarch64*-*-*]
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector btruncf calls.
 
 proc check_effective_target_vect_call_btruncf { } {
     return [check_cached_effective_target_indexed vect_call_btruncf {
-      expr { [istarget aarch64*-*-*] }}]
+      expr { [istarget aarch64*-*-*]
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector ceil calls.
 
 proc check_effective_target_vect_call_ceil { } {
     return [check_cached_effective_target_indexed vect_call_ceil {
-      expr { [istarget aarch64*-*-*] }}]
+      expr { [istarget aarch64*-*-*]
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector ceilf calls.
@@ -6416,7 +6465,8 @@  proc check_effective_target_vect_call_floor { } {
 
 proc check_effective_target_vect_call_floorf { } {
     return [check_cached_effective_target_indexed vect_call_floorf {
-      expr { [istarget aarch64*-*-*] }}]
+      expr { [istarget aarch64*-*-*]
+	     || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector lceil calls.
@@ -7945,7 +7995,8 @@  proc check_effective_target_gld { } {
 # (LTO) support.
 
 proc check_effective_target_lto { } {
-    if { [istarget nvptx-*-*] } {
+    if { [istarget nvptx-*-*]
+	 || [istarget amdgcn-*-*] } {
 	return 0;
     }
     return [check_no_compiler_messages lto object {
@@ -8263,6 +8314,8 @@  proc check_vect_support_and_set_flags { } {
 	    lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
             set dg-do-what-default compile
         }
+    } elseif [istarget amdgcn-*-*] {
+        set dg-do-what-default run
     } else {
         return 0
     }