[v4,0/5] x86: operand size handling improvements

Message ID 6f216bef-df15-383c-cbff-106c9f4b2bb3@suse.com
Headers show
  • x86: operand size handling improvements
Related show


Jan Beulich Feb. 10, 2020, 1:50 p.m.
The main goal continues to be better consistency in the handling of insn
operands, i.e. in particular less unexpected behavior when deducing how
things would behave from observations with one (set of) insn(s) or
operand(s) towards other constructs.

1: x86: also disallow non-byte/-word registers with byte/word suffix
2: x86: move certain MOVSX/MOVZX tests
3: x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX
4: x86: correct VFPCLASSP{S,D} operand size handling
5: x86-64: Intel64 adjustments for insns dealing with far pointers

v4 addresses prior comments, drops 1 patch (leaving aside ones
which simply got committed), and adds 1 new patch. I realize that
patch 5 in particular may need re-basing over "x86: Accept Intel64
only instruction by default", if that goes in earlier.