[0/57,Arm] : Add support for Armv8.1-M Mainline MVE instructions

Message ID 19569550-4d2e-0bb3-592a-d91050d490f6@arm.com
Headers show
Series
  • : Add support for Armv8.1-M Mainline MVE instructions
Related show

Message

Andre Vieira (lists) May 1, 2019, 4:51 p.m.
Hi,

This patch series adds support for all M-profile Vector Extension(MVE) 
instructions to GAS and Objdump.  Their specifications can be found on 
Arm Developer (see https://developer.arm.com/docs/ddi0553/latest).

The patch series is split into three main groups:
- patches 1-36 are GAS patches
- patches 37-56 are OBJDUMP patches
- patch 57 contains all positive testing

The reason to split the testing is because we use assembly macros to 
generate extensive testing, which leads to massive 'expected result' 
files. Which would require zipping most of the patches to be able to 
send them over email. So instead we decided to collate all positive 
testing into one patch and only zip that one. The negative tests are 
smaller and have been included per relevant patch.

The expected value for positive tests have been compared to a different, 
internal implementation.

Cheers,
Andre

Comments

Andre Vieira (lists) May 1, 2019, 5:18 p.m. | #1
Hi,

This patch adds support for MVE instructions VQDMLADH, VQRDMLADH, 
VQDMLSDH, and VQRDMLSDH.

gas/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
         (insns): Add entries for MVE mnemonics.
	* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b5c263688134bcd733c5ba8f93fe003268859abd..abe37b72eacd9c2b4ea2fae113dcd9ab339cb2f5 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17308,6 +17308,28 @@ do_mve_vmulh (void)
   mve_encode_qqq (et.type == NT_unsigned, et.size);
 }
 
+
+static void
+do_mve_vqdmladh (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
+  struct neon_type_el et
+    = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
+
+  if (inst.cond > COND_ALWAYS)
+    inst.pred_insn_type = INSIDE_VPT_INSN;
+  else
+    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+  if (et.size == 32
+      && (inst.operands[0].reg == inst.operands[1].reg
+	  || inst.operands[0].reg == inst.operands[2].reg))
+    as_tsktsk (BAD_MVE_SRCDEST);
+
+  mve_encode_qqq (0, et.size);
+}
+
+
 static void
 do_mve_vmull (void)
 {
@@ -24746,6 +24768,15 @@ static const struct asm_opcode insns[] =
  mToC("vpnot",	  fe310f4d,	0, (),				mve_vpnot),
  mToC("vpsel",	  fe310f01,	3, (RMQ, RMQ, RMQ),		mve_vpsel),
 
+ mToC("vqdmladh",  ee000e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqdmladhx", ee001e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqrdmladh", ee000e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqrdmladhx",ee001e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqdmlsdh",  fe000e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqdmlsdhx", fe001e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqrdmlsdh", fe000e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+ mToC("vqrdmlsdhx",fe001e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
+
 #undef THUMB_VARIANT
 #define THUMB_VARIANT & mve_fp_ext
  mToC("vcmul", ee300e00,   4, (RMQ, RMQ, RMQ, EXPi),		  mve_vcmul),
diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.d b/gas/testsuite/gas/arm/mve-vqdmladh-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..5d37855f075011e8c19deab4e42007cb9e15ad3f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQDMLADH and VQRDMLADH instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqdmladh-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.l b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..96057b8daf64b113188c4b1411372d71d4606f97
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
+[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:14: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
+[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
+[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
+[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:32: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:34: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
+[^:]*:39: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:48: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
+[^:]*:55: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:56: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:58: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
+[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.s b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..7cedb3934b7247e336695caddd792509099073fd
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
@@ -0,0 +1,61 @@
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqdmladh.u32 q0, q1, q2
+vqdmladh.s64 q0, q1, q2
+vqdmladh.s32 q0, q0, q2
+vqdmladh.s32 q0, q1, q0
+vqdmladhx.u32 q0, q1, q2
+vqdmladhx.s64 q0, q1, q2
+vqdmladhx.s32 q0, q0, q2
+vqdmladhx.s32 q0, q1, q0
+vqrdmladh.u32 q0, q1, q2
+vqrdmladh.s64 q0, q1, q2
+vqrdmladh.s32 q0, q0, q2
+vqrdmladh.s32 q0, q1, q0
+vqrdmladhx.u32 q0, q1, q2
+vqrdmladhx.s64 q0, q1, q2
+vqrdmladhx.s32 q0, q0, q2
+vqrdmladhx.s32 q0, q1, q0
+cond vqdmladh
+cond vqdmladhx
+cond vqrdmladh
+cond vqrdmladhx
+it eq
+vqdmladheq.s32 q0, q1, q2
+vqdmladheq.s32 q0, q1, q2
+vpst
+vqdmladheq.s32 q0, q1, q2
+vqdmladht.s32 q0, q1, q2
+vpst
+vqdmladh.s32 q0, q1, q2
+it eq
+vqdmladhxeq.s32 q0, q1, q2
+vqdmladhxeq.s32 q0, q1, q2
+vpst
+vqdmladhxeq.s32 q0, q1, q2
+vqdmladhxt.s32 q0, q1, q2
+vpst
+vqdmladhx.s32 q0, q1, q2
+it eq
+vqrdmladheq.s32 q0, q1, q2
+vqrdmladheq.s32 q0, q1, q2
+vpst
+vqrdmladheq.s32 q0, q1, q2
+vqrdmladht.s32 q0, q1, q2
+vpst
+vqrdmladh.s32 q0, q1, q2
+it eq
+vqrdmladhxeq.s32 q0, q1, q2
+vqrdmladhxeq.s32 q0, q1, q2
+vpst
+vqrdmladhxeq.s32 q0, q1, q2
+vqrdmladhxt.s32 q0, q1, q2
+vpst
+vqrdmladhx.s32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..6da0050fa526bf150830e1f70ee41b6df1413dd0
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQDMLSDH and VQRDMLSDH instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqdmlsdh-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..465476ccc1377d71aea25e42154cb87c6ac9e863
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
+[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:14: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
+[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
+[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
+[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:32: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:34: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
+[^:]*:39: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:48: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
+[^:]*:55: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:56: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:58: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
+[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..4c047a9373aa4b2e6195f0de932117becefde092
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
@@ -0,0 +1,61 @@
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqdmlsdh.u32 q0, q1, q2
+vqdmlsdh.s64 q0, q1, q2
+vqdmlsdh.s32 q0, q0, q2
+vqdmlsdh.s32 q0, q1, q0
+vqdmlsdhx.u32 q0, q1, q2
+vqdmlsdhx.s64 q0, q1, q2
+vqdmlsdhx.s32 q0, q0, q2
+vqdmlsdhx.s32 q0, q1, q0
+vqrdmlsdh.u32 q0, q1, q2
+vqrdmlsdh.s64 q0, q1, q2
+vqrdmlsdh.s32 q0, q0, q2
+vqrdmlsdh.s32 q0, q1, q0
+vqrdmlsdhx.u32 q0, q1, q2
+vqrdmlsdhx.s64 q0, q1, q2
+vqrdmlsdhx.s32 q0, q0, q2
+vqrdmlsdhx.s32 q0, q1, q0
+cond vqdmlsdh
+cond vqdmlsdhx
+cond vqrdmlsdh
+cond vqrdmlsdhx
+it eq
+vqdmlsdheq.s32 q0, q1, q2
+vqdmlsdheq.s32 q0, q1, q2
+vpst
+vqdmlsdheq.s32 q0, q1, q2
+vqdmlsdht.s32 q0, q1, q2
+vpst
+vqdmlsdh.s32 q0, q1, q2
+it eq
+vqdmlsdhxeq.s32 q0, q1, q2
+vqdmlsdhxeq.s32 q0, q1, q2
+vpst
+vqdmlsdhxeq.s32 q0, q1, q2
+vqdmlsdhxt.s32 q0, q1, q2
+vpst
+vqdmlsdhx.s32 q0, q1, q2
+it eq
+vqrdmlsdheq.s32 q0, q1, q2
+vqrdmlsdheq.s32 q0, q1, q2
+vpst
+vqrdmlsdheq.s32 q0, q1, q2
+vqrdmlsdht.s32 q0, q1, q2
+vpst
+vqrdmlsdh.s32 q0, q1, q2
+it eq
+vqrdmlsdhxeq.s32 q0, q1, q2
+vqrdmlsdhxeq.s32 q0, q1, q2
+vpst
+vqrdmlsdhxeq.s32 q0, q1, q2
+vqrdmlsdhxt.s32 q0, q1, q2
+vpst
+vqrdmlsdhx.s32 q0, q1, q2
Andre Vieira (lists) May 1, 2019, 5:47 p.m. | #2
Hello,

This patch adds support for all MVE vector shift instructions.

opcodes/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>
             Michael Collison <michael.collison@arm.com>

	* arm-dis.c (enum mve_instructions): Add new instructions.
	(enum mve_undefined): Add new reasons.
	(is_mve_encoding_conflict): Handle new instructions.
	(is_mve_undefined): Likewise.
	(is_mve_unpredictable): Likewise.
	(print_mve_undefined): Likewise.
	(print_mve_size): Likewise.
	(print_mve_shift_n): Likewise.
	(print_insn_mve): Likewise.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f2e244d104cdb1938ea2a9b8066647b485aaaa1f..56255d5f61dd29b72e02469894186734ca1b4346 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -184,6 +184,30 @@ enum mve_instructions
   MVE_VHCADD,
   MVE_VCMLA_FP,
   MVE_VCMUL_FP,
+  MVE_VQRSHL_T1,
+  MVE_VQRSHL_T2,
+  MVE_VQRSHRN,
+  MVE_VQRSHRUN,
+  MVE_VQSHL_T1,
+  MVE_VQSHL_T2,
+  MVE_VQSHLU_T3,
+  MVE_VQSHL_T4,
+  MVE_VQSHRN,
+  MVE_VQSHRUN,
+  MVE_VRSHL_T1,
+  MVE_VRSHL_T2,
+  MVE_VRSHR,
+  MVE_VRSHRN,
+  MVE_VSHL_T1,
+  MVE_VSHL_T2,
+  MVE_VSHL_T3,
+  MVE_VSHLC,
+  MVE_VSHLL_T1,
+  MVE_VSHLL_T2,
+  MVE_VSHR,
+  MVE_VSHRN,
+  MVE_VSLI,
+  MVE_VSRI,
   MVE_NONE
 };
 
@@ -216,6 +240,7 @@ enum mve_unpredictable
 
 enum mve_undefined
 {
+  UNDEF_SIZE,			/* undefined size.  */
   UNDEF_SIZE_0,			/* undefined because size == 0.  */
   UNDEF_SIZE_2,			/* undefined because size == 2.  */
   UNDEF_SIZE_3,			/* undefined because size == 3.  */
@@ -2420,6 +2445,63 @@ static const struct mopcode32 mve_opcodes[] =
    0xef800050, 0xefb810f0,
    "vorr%v.i%8-11s\t%13-15,22Q, %E"},
 
+  /* Vector VQSHL T2 Variant.
+     NOTE: MVE_VQSHL_T2 must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQSHL_T2,
+   0xef800750, 0xef801fd1,
+   "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VQSHLU T3 Variant
+     NOTE: MVE_VQSHL_T2 must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQSHLU_T3,
+   0xff800650, 0xff801fd1,
+   "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VRSHR
+     NOTE: MVE_VRSHR must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VRSHR,
+   0xef800250, 0xef801fd1,
+   "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VSHL.
+     NOTE: MVE_VSHL must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHL_T1,
+   0xef800550, 0xff801fd1,
+   "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VSHR
+     NOTE: MVE_VSHR must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHR,
+   0xef800050, 0xef801fd1,
+   "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VSLI
+     NOTE: MVE_VSLI must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSLI,
+   0xff800550, 0xff801fd1,
+   "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VSRI
+     NOTE: MVE_VSRI must appear in the table before
+     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSRI,
+   0xff800450, 0xff801fd1,
+   "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
   /* Vector VMOV immediate to vector,
      cmode == 11x1 -> VMVN which is UNDEFINED
      for such a cmode.  */
@@ -2462,6 +2544,13 @@ static const struct mopcode32 mve_opcodes[] =
    0xee100b10, 0xff100f1f,
    "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
 
+  /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
+     to instruction opcode aliasing.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHLL_T1,
+   0xeea00f40, 0xefa00fd1,
+   "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
   /* Vector VMOVL long.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VMOVL,
@@ -2612,6 +2701,54 @@ static const struct mopcode32 mve_opcodes[] =
    0xfe010e60, 0xff811f70,
    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
 
+  /* Vector VQRSHL T1 variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQRSHL_T1,
+   0xef000550, 0xef811f51,
+   "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
+
+  /* Vector VQRSHL T2 variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQRSHL_T2,
+   0xee331ee0, 0xefb31ff0,
+   "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
+
+  /* Vector VQRSHRN.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQRSHRN,
+   0xee800f41, 0xefa00fd1,
+   "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VQRSHRUN.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQRSHRUN,
+   0xfe800fc0, 0xffa00fd1,
+   "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VQSHL T1 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQSHL_T1,
+   0xee311ee0, 0xefb31ff0,
+   "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
+
+  /* Vector VQSHL T4 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQSHL_T4,
+   0xef000450, 0xef811f51,
+   "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
+
+  /* Vector VQSHRN.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQSHRN,
+   0xee800f40, 0xefa00fd1,
+   "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VQSHRUN.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VQSHRUN,
+   0xee800fc0, 0xffa00fd1,
+   "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
   /* Vector VRINT floating point.  */
   {ARM_FEATURE_COPROC (FPU_MVE_FP),
    MVE_VRINT_FP,
@@ -2630,6 +2767,54 @@ static const struct mopcode32 mve_opcodes[] =
    0xee801f00, 0xef811f51,
    "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
 
+  /* Vector VRSHL T1 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VRSHL_T1,
+   0xef000540, 0xef811f51,
+   "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
+
+  /* Vector VRSHL T2 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VRSHL_T2,
+   0xee331e60, 0xefb31ff0,
+   "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
+
+  /* Vector VRSHRN.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VRSHRN,
+   0xfe800fc1, 0xffa00fd1,
+   "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
+  /* Vector VSHL T2 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHL_T2,
+   0xee311e60, 0xefb31ff0,
+   "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
+
+  /* Vector VSHL T3 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHL_T3,
+   0xef000440, 0xef811f51,
+   "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
+
+  /* Vector VSHLC.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHLC,
+   0xeea00fc0, 0xffa01ff0,
+   "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
+
+  /* Vector VSHLL T2 Variant.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHLL_T2,
+   0xee310e01, 0xefb30fd1,
+   "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
+
+  /* Vector VSHRN.  */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VSHRN,
+   0xee800fc1, 0xffa00fd1,
+   "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+
   /* Vector VST2 no writeback.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VST2,
@@ -4734,6 +4919,10 @@ is_mve_encoding_conflict (unsigned long given,
       else
 	return FALSE;
 
+    case MVE_VQRSHL_T1:
+    case MVE_VQSHL_T4:
+    case MVE_VRSHL_T1:
+    case MVE_VSHL_T3:
     case MVE_VCADD_VEC:
     case MVE_VHCADD:
     case MVE_VDDUP:
@@ -4844,6 +5033,11 @@ is_mve_encoding_conflict (unsigned long given,
 	  return FALSE;
       }
 
+    case MVE_VQRSHL_T2:
+    case MVE_VQSHL_T1:
+    case MVE_VRSHL_T2:
+    case MVE_VSHL_T2:
+    case MVE_VSHLL_T2:
     case MVE_VADDV:
     case MVE_VMOVN:
     case MVE_VQMOVUN:
@@ -4876,6 +5070,32 @@ is_mve_encoding_conflict (unsigned long given,
       else
 	return FALSE;
 
+
+    case MVE_VSHLL_T1:
+      if (arm_decode_field (given, 16, 18) == 0)
+	{
+	  unsigned long sz = arm_decode_field (given, 19, 20);
+
+	  if ((sz == 1) || (sz == 2))
+	    return TRUE;
+	  else
+	    return FALSE;
+	}
+      else
+	return FALSE;
+
+    case MVE_VQSHL_T2:
+    case MVE_VQSHLU_T3:
+    case MVE_VRSHR:
+    case MVE_VSHL_T1:
+    case MVE_VSHR:
+    case MVE_VSLI:
+    case MVE_VSRI:
+      if (arm_decode_field (given, 19, 21) == 0)
+	return TRUE;
+      else
+	return FALSE;
+
     default:
       return FALSE;
 
@@ -5231,6 +5451,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       else
 	return FALSE;
 
+    case MVE_VSHLL_T2:
     case MVE_VMOVN:
       if (arm_decode_field (given, 18, 19) == 2)
 	{
@@ -5253,6 +5474,56 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       else
 	return FALSE;
 
+    case MVE_VQSHRN:
+    case MVE_VQSHRUN:
+    case MVE_VSHLL_T1:
+    case MVE_VSHRN:
+      {
+	unsigned long sz = arm_decode_field (given, 19, 20);
+	if (sz == 1)
+	  return FALSE;
+	else if ((sz & 2) == 2)
+	  return FALSE;
+	else
+	  {
+	    *undefined_code = UNDEF_SIZE;
+	    return TRUE;
+	  }
+      }
+      break;
+
+    case MVE_VQSHL_T2:
+    case MVE_VQSHLU_T3:
+    case MVE_VRSHR:
+    case MVE_VSHL_T1:
+    case MVE_VSHR:
+    case MVE_VSLI:
+    case MVE_VSRI:
+      {
+	unsigned long sz = arm_decode_field (given, 19, 21);
+	if ((sz & 7) == 1)
+	  return FALSE;
+	else if ((sz & 6) == 2)
+	  return FALSE;
+	else if ((sz & 4) == 4)
+	  return FALSE;
+	else
+	  {
+	    *undefined_code = UNDEF_SIZE;
+	    return TRUE;
+	  }
+      }
+
+    case MVE_VQRSHRN:
+    case MVE_VQRSHRUN:
+      if (arm_decode_field (given, 19, 20) == 0)
+	{
+	  *undefined_code = UNDEF_SIZE_0;
+	  return TRUE;
+	}
+      else
+	return FALSE;
+
     default:
       return FALSE;
     }
@@ -5312,6 +5583,11 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	return FALSE;
       }
 
+    case MVE_VQRSHL_T2:
+    case MVE_VQSHL_T1:
+    case MVE_VRSHL_T2:
+    case MVE_VSHL_T2:
+    case MVE_VSHLC:
     case MVE_VQDMLAH:
     case MVE_VQRDMLAH:
     case MVE_VQDMLASH:
@@ -5900,6 +6176,10 @@ print_mve_undefined (struct disassemble_info *info,
 
   switch (undefined_code)
     {
+    case UNDEF_SIZE:
+      func (stream, "illegal size");
+      break;
+
     case UNDEF_SIZE_0:
       func (stream, "size equals zero");
       break;
@@ -6406,8 +6686,17 @@ print_mve_size (struct disassemble_info *info,
     case MVE_VQRDMULH_T2:
     case MVE_VQDMULH_T3:
     case MVE_VQRDMULH_T4:
+    case MVE_VQRSHL_T1:
+    case MVE_VQRSHL_T2:
+    case MVE_VQSHL_T1:
+    case MVE_VQSHL_T4:
     case MVE_VRHADD:
     case MVE_VRINT_FP:
+    case MVE_VRSHL_T1:
+    case MVE_VRSHL_T2:
+    case MVE_VSHL_T2:
+    case MVE_VSHL_T3:
+    case MVE_VSHLL_T2:
     case MVE_VST2:
     case MVE_VST4:
     case MVE_VSTRB_SCATTER_T1:
@@ -6566,11 +6855,95 @@ print_mve_size (struct disassemble_info *info,
 	}
       break;
 
+    case MVE_VQSHRN:
+    case MVE_VQSHRUN:
+    case MVE_VQRSHRN:
+    case MVE_VQRSHRUN:
+    case MVE_VRSHRN:
+    case MVE_VSHRN:
+      {
+	switch (size)
+	{
+	case 1:
+	  func (stream, "16");
+	  break;
+
+	case 2: case 3:
+	  func (stream, "32");
+	  break;
+
+	default:
+	  break;
+	}
+      }
+      break;
+
+    case MVE_VQSHL_T2:
+    case MVE_VQSHLU_T3:
+    case MVE_VRSHR:
+    case MVE_VSHL_T1:
+    case MVE_VSHLL_T1:
+    case MVE_VSHR:
+    case MVE_VSLI:
+    case MVE_VSRI:
+      {
+	switch (size)
+	{
+	case 1:
+	  func (stream, "8");
+	  break;
+
+	case 2: case 3:
+	  func (stream, "16");
+	  break;
+
+	case 4: case 5: case 6: case 7:
+	  func (stream, "32");
+	  break;
+
+	default:
+	  break;
+	}
+      }
+      break;
+
     default:
       break;
     }
 }
 
+static void
+print_mve_shift_n (struct disassemble_info *info, long given,
+		   enum mve_instructions matched_insn)
+{
+  void *stream = info->stream;
+  fprintf_ftype func = info->fprintf_func;
+
+  int startAt0
+    = matched_insn == MVE_VQSHL_T2
+      || matched_insn == MVE_VQSHLU_T3
+      || matched_insn == MVE_VSHL_T1
+      || matched_insn == MVE_VSHLL_T1
+      || matched_insn == MVE_VSLI;
+
+  unsigned imm6 = (given & 0x3f0000) >> 16;
+
+  if (matched_insn == MVE_VSHLL_T1)
+    imm6 &= 0x1f;
+
+  unsigned shiftAmount = 0;
+  if ((imm6 & 0x20) != 0)
+    shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
+  else if ((imm6 & 0x10) != 0)
+    shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
+  else if ((imm6 & 0x08) != 0)
+    shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
+  else
+    print_mve_undefined (info, UNDEF_SIZE_0);
+
+  func (stream, "%u", shiftAmount);
+}
+
 static void
 print_vec_condition (struct disassemble_info *info, long given,
 		     enum mve_instructions matched_insn)
@@ -8210,8 +8583,42 @@ print_insn_mve (struct disassemble_info *info, long given)
 			    func (stream, "%s", arm_regnames[value]);
 			    break;
 			  case 'd':
-			    func (stream, "%ld", value);
-			    value_in_comment = value;
+			    if (insn->mve_op == MVE_VQSHL_T2
+				|| insn->mve_op == MVE_VQSHLU_T3
+				|| insn->mve_op == MVE_VRSHR
+				|| insn->mve_op == MVE_VRSHRN
+				|| insn->mve_op == MVE_VSHL_T1
+				|| insn->mve_op == MVE_VSHLL_T1
+				|| insn->mve_op == MVE_VSHR
+				|| insn->mve_op == MVE_VSHRN
+				|| insn->mve_op == MVE_VSLI
+				|| insn->mve_op == MVE_VSRI)
+			      print_mve_shift_n (info, given, insn->mve_op);
+			    else if (insn->mve_op == MVE_VSHLL_T2)
+			      {
+				switch (value)
+				  {
+				  case 0x00:
+				    func (stream, "8");
+				    break;
+				  case 0x01:
+				    func (stream, "16");
+				    break;
+				  case 0x10:
+				    print_mve_undefined (info, UNDEF_SIZE_0);
+				    break;
+				  default:
+				    assert (0);
+				    break;
+				  }
+			      }
+			    else
+			      {
+				if (insn->mve_op == MVE_VSHLC && value == 0)
+				  value = 32;
+				func (stream, "%ld", value);
+				value_in_comment = value;
+			      }
 			    break;
 			  case 'F':
 			    func (stream, "s%ld", value);
Andre Vieira (lists) May 1, 2019, 6:23 p.m. | #3
Hi,

This patch (see attachment) adds all MVE GAS positive tests.


gas/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * testsuite/gas/arm/mve-tailpredloop.d: New test.
         * testsuite/gas/arm/mve-tailpredloop.s: New test.
         * testsuite/gas/arm/mve-vabav.d: New test.
         * testsuite/gas/arm/mve-vabav.s: New test.
         * testsuite/gas/arm/mve-vabd.d: New test.
         * testsuite/gas/arm/mve-vabd.s: New test.
         * testsuite/gas/arm/mve-vabsneg.d: New test.
         * testsuite/gas/arm/mve-vabsneg.s: New test.
         * testsuite/gas/arm/mve-vadc.d: New test.
         * testsuite/gas/arm/mve-vadc.s: New test.
         * testsuite/gas/arm/mve-vaddlv.d: New test.
         * testsuite/gas/arm/mve-vaddlv.s: New test.
         * testsuite/gas/arm/mve-vaddsub.d: New test.
         * testsuite/gas/arm/mve-vaddsub.s: New test.
         * testsuite/gas/arm/mve-vaddv.d: New test.
         * testsuite/gas/arm/mve-vaddv.s: New test.
         * testsuite/gas/arm/mve-vand.d: New test.
         * testsuite/gas/arm/mve-vand.s: New test.
         * testsuite/gas/arm/mve-vbic.d: New test.
         * testsuite/gas/arm/mve-vbic.s: New test.
         * testsuite/gas/arm/mve-vbrsr.d: New test.
         * testsuite/gas/arm/mve-vbrsr.s: New test.
         * testsuite/gas/arm/mve-vcadd.d: New test.
         * testsuite/gas/arm/mve-vcadd.s: New test.
         * testsuite/gas/arm/mve-vcls.d: New test.
         * testsuite/gas/arm/mve-vcls.s: New test.
         * testsuite/gas/arm/mve-vclz.d: New test.
         * testsuite/gas/arm/mve-vclz.s: New test.
         * testsuite/gas/arm/mve-vcmla.d: New test.
         * testsuite/gas/arm/mve-vcmla.s: New test.
         * testsuite/gas/arm/mve-vcmp.d: New test.
         * testsuite/gas/arm/mve-vcmp.s: New test.
         * testsuite/gas/arm/mve-vcmul.d: New test.
         * testsuite/gas/arm/mve-vcmul.s: New test.
         * testsuite/gas/arm/mve-vcvt-1.d: New test.
         * testsuite/gas/arm/mve-vcvt-1.s: New test.
         * testsuite/gas/arm/mve-vcvt-2.d: New test.
         * testsuite/gas/arm/mve-vcvt-2.s: New test.
         * testsuite/gas/arm/mve-vcvt-3.d: New test.
         * testsuite/gas/arm/mve-vcvt-3.s: New test.
         * testsuite/gas/arm/mve-vcvt-4.d: New test.
         * testsuite/gas/arm/mve-vcvt-4.s: New test.
         * testsuite/gas/arm/mve-vddup.d: New test.
         * testsuite/gas/arm/mve-vddup.s: New test.
         * testsuite/gas/arm/mve-vdup.d: New test.
         * testsuite/gas/arm/mve-vdup.s: New test.
         * testsuite/gas/arm/mve-veor.d: New test.
         * testsuite/gas/arm/mve-veor.s: New test.
         * testsuite/gas/arm/mve-vfma-vfms.d: New test.
         * testsuite/gas/arm/mve-vfma-vfms.s: New test.
         * testsuite/gas/arm/mve-vfmas.d: New test.
         * testsuite/gas/arm/mve-vfmas.s: New test.
         * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.
         * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.
         * testsuite/gas/arm/mve-vhcadd.d: New test.
         * testsuite/gas/arm/mve-vhcadd.s: New test.
         * testsuite/gas/arm/mve-vmax-vmin.d: New test.
         * testsuite/gas/arm/mve-vmax-vmin.s: New test.
         * testsuite/gas/arm/mve-vmaxa-vmina.d: New test.
         * testsuite/gas/arm/mve-vmaxa-vmina.s: New test.
         * testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.
         * testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.
         * testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.
         * testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.
         * testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.
         * testsuite/gas/arm/mve-vmaxv-vminv.d: New test.
         * testsuite/gas/arm/mve-vmaxv-vminv.s: New test.
         * testsuite/gas/arm/mve-vmla.d: New test.
         * testsuite/gas/arm/mve-vmla.s: New test.
         * testsuite/gas/arm/mve-vmladav.d: New test.
         * testsuite/gas/arm/mve-vmladav.s: New test.
         * testsuite/gas/arm/mve-vmlaldav.d: New test.
         * testsuite/gas/arm/mve-vmlaldav.s: New test.
         * testsuite/gas/arm/mve-vmlalv.d: New test.
         * testsuite/gas/arm/mve-vmlalv.s: New test.
         * testsuite/gas/arm/mve-vmlas.d: New test.
         * testsuite/gas/arm/mve-vmlas.s: New test.
         * testsuite/gas/arm/mve-vmlav.d: New test.
         * testsuite/gas/arm/mve-vmlav.s: New test.
         * testsuite/gas/arm/mve-vmlsdav.d: New test.
         * testsuite/gas/arm/mve-vmlsdav.s: New test.
         * testsuite/gas/arm/mve-vmlsldav.d: New test.
         * testsuite/gas/arm/mve-vmlsldav.s: New test.
         * testsuite/gas/arm/mve-vmov-1.d: New test.
         * testsuite/gas/arm/mve-vmov-1.s: New test.
         * testsuite/gas/arm/mve-vmov-2.d: New test.
         * testsuite/gas/arm/mve-vmov-2.s: New test.
         * testsuite/gas/arm/mve-vmul.d: New test.
         * testsuite/gas/arm/mve-vmul.s: New test.
         * testsuite/gas/arm/mve-vmulh.d: New test.
         * testsuite/gas/arm/mve-vmulh.s: New test.
         * testsuite/gas/arm/mve-vmullbt.d: New test.
         * testsuite/gas/arm/mve-vmullbt.s: New test.
         * testsuite/gas/arm/mve-vmvn.d: New test.
         * testsuite/gas/arm/mve-vmvn.s: New test.
         * testsuite/gas/arm/mve-vorn.d: New test.
         * testsuite/gas/arm/mve-vorn.s: New test.
         * testsuite/gas/arm/mve-vorr.d: New test.
         * testsuite/gas/arm/mve-vorr.s: New test.
         * testsuite/gas/arm/mve-vpnot.d: New test.
         * testsuite/gas/arm/mve-vpnot.s: New test.
         * testsuite/gas/arm/mve-vpsel.d: New test.
         * testsuite/gas/arm/mve-vpsel.s: New test.
         * testsuite/gas/arm/mve-vpt.d: New test.
         * testsuite/gas/arm/mve-vpt.s: New test.
         * testsuite/gas/arm/mve-vqabsneg.s: New test.
         * testsuite/gas/arm/mve-vqaddsub.d: New test.
         * testsuite/gas/arm/mve-vqaddsub.s: New test.
         * testsuite/gas/arm/mve-vqdmladh.d: New test.
         * testsuite/gas/arm/mve-vqdmladh.s: New test.
         * testsuite/gas/arm/mve-vqdmlah.d: New test.
         * testsuite/gas/arm/mve-vqdmlah.s: New test.
         * testsuite/gas/arm/mve-vqdmlash.d: New test.
         * testsuite/gas/arm/mve-vqdmlash.s: New test.
         * testsuite/gas/arm/mve-vqdmlsdh.d: New test.
         * testsuite/gas/arm/mve-vqdmlsdh.s: New test.
         * testsuite/gas/arm/mve-vqdmulh.d: New test.
         * testsuite/gas/arm/mve-vqdmulh.s: New test.
         * testsuite/gas/arm/mve-vqdmull.d: New test.
         * testsuite/gas/arm/mve-vqdmull.s: New test.
         * testsuite/gas/arm/mve-vqmovn.d: New test.
         * testsuite/gas/arm/mve-vqmovn.s: New test.
         * testsuite/gas/arm/mve-vqrshl.d: New test.
         * testsuite/gas/arm/mve-vqrshl.s: New test.
         * testsuite/gas/arm/mve-vqrshrn.d: New test.
         * testsuite/gas/arm/mve-vqrshrn.s: New test.
         * testsuite/gas/arm/mve-vqshl.d: New test.
         * testsuite/gas/arm/mve-vqshl.s: New test.
         * testsuite/gas/arm/mve-vrev.d: New test.
         * testsuite/gas/arm/mve-vrev.s: New test.
         * testsuite/gas/arm/mve-vrint.d: New test.
         * testsuite/gas/arm/mve-vrint.s: New test.
         * testsuite/gas/arm/mve-vrmlaldavh.d: New test.
         * testsuite/gas/arm/mve-vrmlaldavh.s: New test.
         * testsuite/gas/arm/mve-vrshl.d: New test.
         * testsuite/gas/arm/mve-vrshl.s: New test.
         * testsuite/gas/arm/mve-vsbc.d: New test.
         * testsuite/gas/arm/mve-vsbc.s: New test.
         * testsuite/gas/arm/mve-vshl.d: New test.
         * testsuite/gas/arm/mve-vshl.s: New test.
         * testsuite/gas/arm/mve-vshlc.d: New test.
         * testsuite/gas/arm/mve-vshlc.s: New test.
         * testsuite/gas/arm/mve-vshll.d: New test.
         * testsuite/gas/arm/mve-vshll.s: New test.
         * testsuite/gas/arm/mve-vshr.d: New test.
         * testsuite/gas/arm/mve-vshr.s: New test.
         * testsuite/gas/arm/mve-vshrn.d: New test.
         * testsuite/gas/arm/mve-vshrn.s: New test.
         * testsuite/gas/arm/mve-vsli.d: New test.
         * testsuite/gas/arm/mve-vsli.s: New test.
         * testsuite/gas/arm/mve-vsri.d: New test.
         * testsuite/gas/arm/mve-vsri.s: New test.
         * testsuite/gas/arm/mve-vstld.d: New test.
         * testsuite/gas/arm/mve-vstld.s: New test.
         * testsuite/gas/arm/mve-vstrldr-1.d: New test.
         * testsuite/gas/arm/mve-vstrldr-1.s: New test.
         * testsuite/gas/arm/mve-vstrldr-2.d: New test.
         * testsuite/gas/arm/mve-vstrldr-2.s: New test.
         * testsuite/gas/arm/mve-vstrldr-3.d: New test.
         * testsuite/gas/arm/mve-vstrldr-3.s: New test.
Andre Vieira (lists) May 1, 2019, 6:24 p.m. | #4
1/4

On 01/05/2019 19:23, Andre Vieira (lists) wrote:
> Hi,

> 

> This patch (see attachment) adds all MVE GAS positive tests.

> 

> 

> gas/ChangeLog:

> 

> 2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>          * testsuite/gas/arm/mve-tailpredloop.d: New test.

>          * testsuite/gas/arm/mve-tailpredloop.s: New test.

>          * testsuite/gas/arm/mve-vabav.d: New test.

>          * testsuite/gas/arm/mve-vabav.s: New test.

>          * testsuite/gas/arm/mve-vabd.d: New test.

>          * testsuite/gas/arm/mve-vabd.s: New test.

>          * testsuite/gas/arm/mve-vabsneg.d: New test.

>          * testsuite/gas/arm/mve-vabsneg.s: New test.

>          * testsuite/gas/arm/mve-vadc.d: New test.

>          * testsuite/gas/arm/mve-vadc.s: New test.

>          * testsuite/gas/arm/mve-vaddlv.d: New test.

>          * testsuite/gas/arm/mve-vaddlv.s: New test.

>          * testsuite/gas/arm/mve-vaddsub.d: New test.

>          * testsuite/gas/arm/mve-vaddsub.s: New test.

>          * testsuite/gas/arm/mve-vaddv.d: New test.

>          * testsuite/gas/arm/mve-vaddv.s: New test.

>          * testsuite/gas/arm/mve-vand.d: New test.

>          * testsuite/gas/arm/mve-vand.s: New test.

>          * testsuite/gas/arm/mve-vbic.d: New test.

>          * testsuite/gas/arm/mve-vbic.s: New test.

>          * testsuite/gas/arm/mve-vbrsr.d: New test.

>          * testsuite/gas/arm/mve-vbrsr.s: New test.

>          * testsuite/gas/arm/mve-vcadd.d: New test.

>          * testsuite/gas/arm/mve-vcadd.s: New test.

>          * testsuite/gas/arm/mve-vcls.d: New test.

>          * testsuite/gas/arm/mve-vcls.s: New test.

>          * testsuite/gas/arm/mve-vclz.d: New test.

>          * testsuite/gas/arm/mve-vclz.s: New test.

>          * testsuite/gas/arm/mve-vcmla.d: New test.

>          * testsuite/gas/arm/mve-vcmla.s: New test.

>          * testsuite/gas/arm/mve-vcmp.d: New test.

>          * testsuite/gas/arm/mve-vcmp.s: New test.

>          * testsuite/gas/arm/mve-vcmul.d: New test.

>          * testsuite/gas/arm/mve-vcmul.s: New test.

>          * testsuite/gas/arm/mve-vcvt-1.d: New test.

>          * testsuite/gas/arm/mve-vcvt-1.s: New test.

>          * testsuite/gas/arm/mve-vcvt-2.d: New test.

>          * testsuite/gas/arm/mve-vcvt-2.s: New test.

>          * testsuite/gas/arm/mve-vcvt-3.d: New test.

>          * testsuite/gas/arm/mve-vcvt-3.s: New test.

>          * testsuite/gas/arm/mve-vcvt-4.d: New test.

>          * testsuite/gas/arm/mve-vcvt-4.s: New test.

>          * testsuite/gas/arm/mve-vddup.d: New test.

>          * testsuite/gas/arm/mve-vddup.s: New test.

>          * testsuite/gas/arm/mve-vdup.d: New test.

>          * testsuite/gas/arm/mve-vdup.s: New test.

>          * testsuite/gas/arm/mve-veor.d: New test.

>          * testsuite/gas/arm/mve-veor.s: New test.

>          * testsuite/gas/arm/mve-vfma-vfms.d: New test.

>          * testsuite/gas/arm/mve-vfma-vfms.s: New test.

>          * testsuite/gas/arm/mve-vfmas.d: New test.

>          * testsuite/gas/arm/mve-vfmas.s: New test.

>          * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.

>          * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.

>          * testsuite/gas/arm/mve-vhcadd.d: New test.

>          * testsuite/gas/arm/mve-vhcadd.s: New test.

>          * testsuite/gas/arm/mve-vmax-vmin.d: New test.

>          * testsuite/gas/arm/mve-vmax-vmin.s: New test.

>          * testsuite/gas/arm/mve-vmaxa-vmina.d: New test.

>          * testsuite/gas/arm/mve-vmaxa-vmina.s: New test.

>          * testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.

>          * testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.

>          * testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.

>          * testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.

>          * testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.

>          * testsuite/gas/arm/mve-vmaxv-vminv.d: New test.

>          * testsuite/gas/arm/mve-vmaxv-vminv.s: New test.

>          * testsuite/gas/arm/mve-vmla.d: New test.

>          * testsuite/gas/arm/mve-vmla.s: New test.

>          * testsuite/gas/arm/mve-vmladav.d: New test.

>          * testsuite/gas/arm/mve-vmladav.s: New test.

>          * testsuite/gas/arm/mve-vmlaldav.d: New test.

>          * testsuite/gas/arm/mve-vmlaldav.s: New test.

>          * testsuite/gas/arm/mve-vmlalv.d: New test.

>          * testsuite/gas/arm/mve-vmlalv.s: New test.

>          * testsuite/gas/arm/mve-vmlas.d: New test.

>          * testsuite/gas/arm/mve-vmlas.s: New test.

>          * testsuite/gas/arm/mve-vmlav.d: New test.

>          * testsuite/gas/arm/mve-vmlav.s: New test.

>          * testsuite/gas/arm/mve-vmlsdav.d: New test.

>          * testsuite/gas/arm/mve-vmlsdav.s: New test.

>          * testsuite/gas/arm/mve-vmlsldav.d: New test.

>          * testsuite/gas/arm/mve-vmlsldav.s: New test.

>          * testsuite/gas/arm/mve-vmov-1.d: New test.

>          * testsuite/gas/arm/mve-vmov-1.s: New test.

>          * testsuite/gas/arm/mve-vmov-2.d: New test.

>          * testsuite/gas/arm/mve-vmov-2.s: New test.

>          * testsuite/gas/arm/mve-vmul.d: New test.

>          * testsuite/gas/arm/mve-vmul.s: New test.

>          * testsuite/gas/arm/mve-vmulh.d: New test.

>          * testsuite/gas/arm/mve-vmulh.s: New test.

>          * testsuite/gas/arm/mve-vmullbt.d: New test.

>          * testsuite/gas/arm/mve-vmullbt.s: New test.

>          * testsuite/gas/arm/mve-vmvn.d: New test.

>          * testsuite/gas/arm/mve-vmvn.s: New test.

>          * testsuite/gas/arm/mve-vorn.d: New test.

>          * testsuite/gas/arm/mve-vorn.s: New test.

>          * testsuite/gas/arm/mve-vorr.d: New test.

>          * testsuite/gas/arm/mve-vorr.s: New test.

>          * testsuite/gas/arm/mve-vpnot.d: New test.

>          * testsuite/gas/arm/mve-vpnot.s: New test.

>          * testsuite/gas/arm/mve-vpsel.d: New test.

>          * testsuite/gas/arm/mve-vpsel.s: New test.

>          * testsuite/gas/arm/mve-vpt.d: New test.

>          * testsuite/gas/arm/mve-vpt.s: New test.

>          * testsuite/gas/arm/mve-vqabsneg.s: New test.

>          * testsuite/gas/arm/mve-vqaddsub.d: New test.

>          * testsuite/gas/arm/mve-vqaddsub.s: New test.

>          * testsuite/gas/arm/mve-vqdmladh.d: New test.

>          * testsuite/gas/arm/mve-vqdmladh.s: New test.

>          * testsuite/gas/arm/mve-vqdmlah.d: New test.

>          * testsuite/gas/arm/mve-vqdmlah.s: New test.

>          * testsuite/gas/arm/mve-vqdmlash.d: New test.

>          * testsuite/gas/arm/mve-vqdmlash.s: New test.

>          * testsuite/gas/arm/mve-vqdmlsdh.d: New test.

>          * testsuite/gas/arm/mve-vqdmlsdh.s: New test.

>          * testsuite/gas/arm/mve-vqdmulh.d: New test.

>          * testsuite/gas/arm/mve-vqdmulh.s: New test.

>          * testsuite/gas/arm/mve-vqdmull.d: New test.

>          * testsuite/gas/arm/mve-vqdmull.s: New test.

>          * testsuite/gas/arm/mve-vqmovn.d: New test.

>          * testsuite/gas/arm/mve-vqmovn.s: New test.

>          * testsuite/gas/arm/mve-vqrshl.d: New test.

>          * testsuite/gas/arm/mve-vqrshl.s: New test.

>          * testsuite/gas/arm/mve-vqrshrn.d: New test.

>          * testsuite/gas/arm/mve-vqrshrn.s: New test.

>          * testsuite/gas/arm/mve-vqshl.d: New test.

>          * testsuite/gas/arm/mve-vqshl.s: New test.

>          * testsuite/gas/arm/mve-vrev.d: New test.

>          * testsuite/gas/arm/mve-vrev.s: New test.

>          * testsuite/gas/arm/mve-vrint.d: New test.

>          * testsuite/gas/arm/mve-vrint.s: New test.

>          * testsuite/gas/arm/mve-vrmlaldavh.d: New test.

>          * testsuite/gas/arm/mve-vrmlaldavh.s: New test.

>          * testsuite/gas/arm/mve-vrshl.d: New test.

>          * testsuite/gas/arm/mve-vrshl.s: New test.

>          * testsuite/gas/arm/mve-vsbc.d: New test.

>          * testsuite/gas/arm/mve-vsbc.s: New test.

>          * testsuite/gas/arm/mve-vshl.d: New test.

>          * testsuite/gas/arm/mve-vshl.s: New test.

>          * testsuite/gas/arm/mve-vshlc.d: New test.

>          * testsuite/gas/arm/mve-vshlc.s: New test.

>          * testsuite/gas/arm/mve-vshll.d: New test.

>          * testsuite/gas/arm/mve-vshll.s: New test.

>          * testsuite/gas/arm/mve-vshr.d: New test.

>          * testsuite/gas/arm/mve-vshr.s: New test.

>          * testsuite/gas/arm/mve-vshrn.d: New test.

>          * testsuite/gas/arm/mve-vshrn.s: New test.

>          * testsuite/gas/arm/mve-vsli.d: New test.

>          * testsuite/gas/arm/mve-vsli.s: New test.

>          * testsuite/gas/arm/mve-vsri.d: New test.

>          * testsuite/gas/arm/mve-vsri.s: New test.

>          * testsuite/gas/arm/mve-vstld.d: New test.

>          * testsuite/gas/arm/mve-vstld.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-1.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-1.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-2.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-2.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-3.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-3.s: New test.
Andre Vieira (lists) May 1, 2019, 6:24 p.m. | #5
2/4

On 01/05/2019 19:23, Andre Vieira (lists) wrote:
> Hi,

> 

> This patch (see attachment) adds all MVE GAS positive tests.

> 

> 

> gas/ChangeLog:

> 

> 2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>          * testsuite/gas/arm/mve-tailpredloop.d: New test.

>          * testsuite/gas/arm/mve-tailpredloop.s: New test.

>          * testsuite/gas/arm/mve-vabav.d: New test.

>          * testsuite/gas/arm/mve-vabav.s: New test.

>          * testsuite/gas/arm/mve-vabd.d: New test.

>          * testsuite/gas/arm/mve-vabd.s: New test.

>          * testsuite/gas/arm/mve-vabsneg.d: New test.

>          * testsuite/gas/arm/mve-vabsneg.s: New test.

>          * testsuite/gas/arm/mve-vadc.d: New test.

>          * testsuite/gas/arm/mve-vadc.s: New test.

>          * testsuite/gas/arm/mve-vaddlv.d: New test.

>          * testsuite/gas/arm/mve-vaddlv.s: New test.

>          * testsuite/gas/arm/mve-vaddsub.d: New test.

>          * testsuite/gas/arm/mve-vaddsub.s: New test.

>          * testsuite/gas/arm/mve-vaddv.d: New test.

>          * testsuite/gas/arm/mve-vaddv.s: New test.

>          * testsuite/gas/arm/mve-vand.d: New test.

>          * testsuite/gas/arm/mve-vand.s: New test.

>          * testsuite/gas/arm/mve-vbic.d: New test.

>          * testsuite/gas/arm/mve-vbic.s: New test.

>          * testsuite/gas/arm/mve-vbrsr.d: New test.

>          * testsuite/gas/arm/mve-vbrsr.s: New test.

>          * testsuite/gas/arm/mve-vcadd.d: New test.

>          * testsuite/gas/arm/mve-vcadd.s: New test.

>          * testsuite/gas/arm/mve-vcls.d: New test.

>          * testsuite/gas/arm/mve-vcls.s: New test.

>          * testsuite/gas/arm/mve-vclz.d: New test.

>          * testsuite/gas/arm/mve-vclz.s: New test.

>          * testsuite/gas/arm/mve-vcmla.d: New test.

>          * testsuite/gas/arm/mve-vcmla.s: New test.

>          * testsuite/gas/arm/mve-vcmp.d: New test.

>          * testsuite/gas/arm/mve-vcmp.s: New test.

>          * testsuite/gas/arm/mve-vcmul.d: New test.

>          * testsuite/gas/arm/mve-vcmul.s: New test.

>          * testsuite/gas/arm/mve-vcvt-1.d: New test.

>          * testsuite/gas/arm/mve-vcvt-1.s: New test.

>          * testsuite/gas/arm/mve-vcvt-2.d: New test.

>          * testsuite/gas/arm/mve-vcvt-2.s: New test.

>          * testsuite/gas/arm/mve-vcvt-3.d: New test.

>          * testsuite/gas/arm/mve-vcvt-3.s: New test.

>          * testsuite/gas/arm/mve-vcvt-4.d: New test.

>          * testsuite/gas/arm/mve-vcvt-4.s: New test.

>          * testsuite/gas/arm/mve-vddup.d: New test.

>          * testsuite/gas/arm/mve-vddup.s: New test.

>          * testsuite/gas/arm/mve-vdup.d: New test.

>          * testsuite/gas/arm/mve-vdup.s: New test.

>          * testsuite/gas/arm/mve-veor.d: New test.

>          * testsuite/gas/arm/mve-veor.s: New test.

>          * testsuite/gas/arm/mve-vfma-vfms.d: New test.

>          * testsuite/gas/arm/mve-vfma-vfms.s: New test.

>          * testsuite/gas/arm/mve-vfmas.d: New test.

>          * testsuite/gas/arm/mve-vfmas.s: New test.

>          * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.

>          * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.

>          * testsuite/gas/arm/mve-vhcadd.d: New test.

>          * testsuite/gas/arm/mve-vhcadd.s: New test.

>          * testsuite/gas/arm/mve-vmax-vmin.d: New test.

>          * testsuite/gas/arm/mve-vmax-vmin.s: New test.

>          * testsuite/gas/arm/mve-vmaxa-vmina.d: New test.

>          * testsuite/gas/arm/mve-vmaxa-vmina.s: New test.

>          * testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.

>          * testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.

>          * testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.

>          * testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.

>          * testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.

>          * testsuite/gas/arm/mve-vmaxv-vminv.d: New test.

>          * testsuite/gas/arm/mve-vmaxv-vminv.s: New test.

>          * testsuite/gas/arm/mve-vmla.d: New test.

>          * testsuite/gas/arm/mve-vmla.s: New test.

>          * testsuite/gas/arm/mve-vmladav.d: New test.

>          * testsuite/gas/arm/mve-vmladav.s: New test.

>          * testsuite/gas/arm/mve-vmlaldav.d: New test.

>          * testsuite/gas/arm/mve-vmlaldav.s: New test.

>          * testsuite/gas/arm/mve-vmlalv.d: New test.

>          * testsuite/gas/arm/mve-vmlalv.s: New test.

>          * testsuite/gas/arm/mve-vmlas.d: New test.

>          * testsuite/gas/arm/mve-vmlas.s: New test.

>          * testsuite/gas/arm/mve-vmlav.d: New test.

>          * testsuite/gas/arm/mve-vmlav.s: New test.

>          * testsuite/gas/arm/mve-vmlsdav.d: New test.

>          * testsuite/gas/arm/mve-vmlsdav.s: New test.

>          * testsuite/gas/arm/mve-vmlsldav.d: New test.

>          * testsuite/gas/arm/mve-vmlsldav.s: New test.

>          * testsuite/gas/arm/mve-vmov-1.d: New test.

>          * testsuite/gas/arm/mve-vmov-1.s: New test.

>          * testsuite/gas/arm/mve-vmov-2.d: New test.

>          * testsuite/gas/arm/mve-vmov-2.s: New test.

>          * testsuite/gas/arm/mve-vmul.d: New test.

>          * testsuite/gas/arm/mve-vmul.s: New test.

>          * testsuite/gas/arm/mve-vmulh.d: New test.

>          * testsuite/gas/arm/mve-vmulh.s: New test.

>          * testsuite/gas/arm/mve-vmullbt.d: New test.

>          * testsuite/gas/arm/mve-vmullbt.s: New test.

>          * testsuite/gas/arm/mve-vmvn.d: New test.

>          * testsuite/gas/arm/mve-vmvn.s: New test.

>          * testsuite/gas/arm/mve-vorn.d: New test.

>          * testsuite/gas/arm/mve-vorn.s: New test.

>          * testsuite/gas/arm/mve-vorr.d: New test.

>          * testsuite/gas/arm/mve-vorr.s: New test.

>          * testsuite/gas/arm/mve-vpnot.d: New test.

>          * testsuite/gas/arm/mve-vpnot.s: New test.

>          * testsuite/gas/arm/mve-vpsel.d: New test.

>          * testsuite/gas/arm/mve-vpsel.s: New test.

>          * testsuite/gas/arm/mve-vpt.d: New test.

>          * testsuite/gas/arm/mve-vpt.s: New test.

>          * testsuite/gas/arm/mve-vqabsneg.s: New test.

>          * testsuite/gas/arm/mve-vqaddsub.d: New test.

>          * testsuite/gas/arm/mve-vqaddsub.s: New test.

>          * testsuite/gas/arm/mve-vqdmladh.d: New test.

>          * testsuite/gas/arm/mve-vqdmladh.s: New test.

>          * testsuite/gas/arm/mve-vqdmlah.d: New test.

>          * testsuite/gas/arm/mve-vqdmlah.s: New test.

>          * testsuite/gas/arm/mve-vqdmlash.d: New test.

>          * testsuite/gas/arm/mve-vqdmlash.s: New test.

>          * testsuite/gas/arm/mve-vqdmlsdh.d: New test.

>          * testsuite/gas/arm/mve-vqdmlsdh.s: New test.

>          * testsuite/gas/arm/mve-vqdmulh.d: New test.

>          * testsuite/gas/arm/mve-vqdmulh.s: New test.

>          * testsuite/gas/arm/mve-vqdmull.d: New test.

>          * testsuite/gas/arm/mve-vqdmull.s: New test.

>          * testsuite/gas/arm/mve-vqmovn.d: New test.

>          * testsuite/gas/arm/mve-vqmovn.s: New test.

>          * testsuite/gas/arm/mve-vqrshl.d: New test.

>          * testsuite/gas/arm/mve-vqrshl.s: New test.

>          * testsuite/gas/arm/mve-vqrshrn.d: New test.

>          * testsuite/gas/arm/mve-vqrshrn.s: New test.

>          * testsuite/gas/arm/mve-vqshl.d: New test.

>          * testsuite/gas/arm/mve-vqshl.s: New test.

>          * testsuite/gas/arm/mve-vrev.d: New test.

>          * testsuite/gas/arm/mve-vrev.s: New test.

>          * testsuite/gas/arm/mve-vrint.d: New test.

>          * testsuite/gas/arm/mve-vrint.s: New test.

>          * testsuite/gas/arm/mve-vrmlaldavh.d: New test.

>          * testsuite/gas/arm/mve-vrmlaldavh.s: New test.

>          * testsuite/gas/arm/mve-vrshl.d: New test.

>          * testsuite/gas/arm/mve-vrshl.s: New test.

>          * testsuite/gas/arm/mve-vsbc.d: New test.

>          * testsuite/gas/arm/mve-vsbc.s: New test.

>          * testsuite/gas/arm/mve-vshl.d: New test.

>          * testsuite/gas/arm/mve-vshl.s: New test.

>          * testsuite/gas/arm/mve-vshlc.d: New test.

>          * testsuite/gas/arm/mve-vshlc.s: New test.

>          * testsuite/gas/arm/mve-vshll.d: New test.

>          * testsuite/gas/arm/mve-vshll.s: New test.

>          * testsuite/gas/arm/mve-vshr.d: New test.

>          * testsuite/gas/arm/mve-vshr.s: New test.

>          * testsuite/gas/arm/mve-vshrn.d: New test.

>          * testsuite/gas/arm/mve-vshrn.s: New test.

>          * testsuite/gas/arm/mve-vsli.d: New test.

>          * testsuite/gas/arm/mve-vsli.s: New test.

>          * testsuite/gas/arm/mve-vsri.d: New test.

>          * testsuite/gas/arm/mve-vsri.s: New test.

>          * testsuite/gas/arm/mve-vstld.d: New test.

>          * testsuite/gas/arm/mve-vstld.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-1.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-1.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-2.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-2.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-3.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-3.s: New test.
Andre Vieira (lists) May 1, 2019, 6:25 p.m. | #6
4/4 EOF :)

On 01/05/2019 19:23, Andre Vieira (lists) wrote:
> Hi,

> 

> This patch (see attachment) adds all MVE GAS positive tests.

> 

> 

> gas/ChangeLog:

> 

> 2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

> 

>          * testsuite/gas/arm/mve-tailpredloop.d: New test.

>          * testsuite/gas/arm/mve-tailpredloop.s: New test.

>          * testsuite/gas/arm/mve-vabav.d: New test.

>          * testsuite/gas/arm/mve-vabav.s: New test.

>          * testsuite/gas/arm/mve-vabd.d: New test.

>          * testsuite/gas/arm/mve-vabd.s: New test.

>          * testsuite/gas/arm/mve-vabsneg.d: New test.

>          * testsuite/gas/arm/mve-vabsneg.s: New test.

>          * testsuite/gas/arm/mve-vadc.d: New test.

>          * testsuite/gas/arm/mve-vadc.s: New test.

>          * testsuite/gas/arm/mve-vaddlv.d: New test.

>          * testsuite/gas/arm/mve-vaddlv.s: New test.

>          * testsuite/gas/arm/mve-vaddsub.d: New test.

>          * testsuite/gas/arm/mve-vaddsub.s: New test.

>          * testsuite/gas/arm/mve-vaddv.d: New test.

>          * testsuite/gas/arm/mve-vaddv.s: New test.

>          * testsuite/gas/arm/mve-vand.d: New test.

>          * testsuite/gas/arm/mve-vand.s: New test.

>          * testsuite/gas/arm/mve-vbic.d: New test.

>          * testsuite/gas/arm/mve-vbic.s: New test.

>          * testsuite/gas/arm/mve-vbrsr.d: New test.

>          * testsuite/gas/arm/mve-vbrsr.s: New test.

>          * testsuite/gas/arm/mve-vcadd.d: New test.

>          * testsuite/gas/arm/mve-vcadd.s: New test.

>          * testsuite/gas/arm/mve-vcls.d: New test.

>          * testsuite/gas/arm/mve-vcls.s: New test.

>          * testsuite/gas/arm/mve-vclz.d: New test.

>          * testsuite/gas/arm/mve-vclz.s: New test.

>          * testsuite/gas/arm/mve-vcmla.d: New test.

>          * testsuite/gas/arm/mve-vcmla.s: New test.

>          * testsuite/gas/arm/mve-vcmp.d: New test.

>          * testsuite/gas/arm/mve-vcmp.s: New test.

>          * testsuite/gas/arm/mve-vcmul.d: New test.

>          * testsuite/gas/arm/mve-vcmul.s: New test.

>          * testsuite/gas/arm/mve-vcvt-1.d: New test.

>          * testsuite/gas/arm/mve-vcvt-1.s: New test.

>          * testsuite/gas/arm/mve-vcvt-2.d: New test.

>          * testsuite/gas/arm/mve-vcvt-2.s: New test.

>          * testsuite/gas/arm/mve-vcvt-3.d: New test.

>          * testsuite/gas/arm/mve-vcvt-3.s: New test.

>          * testsuite/gas/arm/mve-vcvt-4.d: New test.

>          * testsuite/gas/arm/mve-vcvt-4.s: New test.

>          * testsuite/gas/arm/mve-vddup.d: New test.

>          * testsuite/gas/arm/mve-vddup.s: New test.

>          * testsuite/gas/arm/mve-vdup.d: New test.

>          * testsuite/gas/arm/mve-vdup.s: New test.

>          * testsuite/gas/arm/mve-veor.d: New test.

>          * testsuite/gas/arm/mve-veor.s: New test.

>          * testsuite/gas/arm/mve-vfma-vfms.d: New test.

>          * testsuite/gas/arm/mve-vfma-vfms.s: New test.

>          * testsuite/gas/arm/mve-vfmas.d: New test.

>          * testsuite/gas/arm/mve-vfmas.s: New test.

>          * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.

>          * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.

>          * testsuite/gas/arm/mve-vhcadd.d: New test.

>          * testsuite/gas/arm/mve-vhcadd.s: New test.

>          * testsuite/gas/arm/mve-vmax-vmin.d: New test.

>          * testsuite/gas/arm/mve-vmax-vmin.s: New test.

>          * testsuite/gas/arm/mve-vmaxa-vmina.d: New test.

>          * testsuite/gas/arm/mve-vmaxa-vmina.s: New test.

>          * testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.

>          * testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.

>          * testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.

>          * testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.

>          * testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.

>          * testsuite/gas/arm/mve-vmaxv-vminv.d: New test.

>          * testsuite/gas/arm/mve-vmaxv-vminv.s: New test.

>          * testsuite/gas/arm/mve-vmla.d: New test.

>          * testsuite/gas/arm/mve-vmla.s: New test.

>          * testsuite/gas/arm/mve-vmladav.d: New test.

>          * testsuite/gas/arm/mve-vmladav.s: New test.

>          * testsuite/gas/arm/mve-vmlaldav.d: New test.

>          * testsuite/gas/arm/mve-vmlaldav.s: New test.

>          * testsuite/gas/arm/mve-vmlalv.d: New test.

>          * testsuite/gas/arm/mve-vmlalv.s: New test.

>          * testsuite/gas/arm/mve-vmlas.d: New test.

>          * testsuite/gas/arm/mve-vmlas.s: New test.

>          * testsuite/gas/arm/mve-vmlav.d: New test.

>          * testsuite/gas/arm/mve-vmlav.s: New test.

>          * testsuite/gas/arm/mve-vmlsdav.d: New test.

>          * testsuite/gas/arm/mve-vmlsdav.s: New test.

>          * testsuite/gas/arm/mve-vmlsldav.d: New test.

>          * testsuite/gas/arm/mve-vmlsldav.s: New test.

>          * testsuite/gas/arm/mve-vmov-1.d: New test.

>          * testsuite/gas/arm/mve-vmov-1.s: New test.

>          * testsuite/gas/arm/mve-vmov-2.d: New test.

>          * testsuite/gas/arm/mve-vmov-2.s: New test.

>          * testsuite/gas/arm/mve-vmul.d: New test.

>          * testsuite/gas/arm/mve-vmul.s: New test.

>          * testsuite/gas/arm/mve-vmulh.d: New test.

>          * testsuite/gas/arm/mve-vmulh.s: New test.

>          * testsuite/gas/arm/mve-vmullbt.d: New test.

>          * testsuite/gas/arm/mve-vmullbt.s: New test.

>          * testsuite/gas/arm/mve-vmvn.d: New test.

>          * testsuite/gas/arm/mve-vmvn.s: New test.

>          * testsuite/gas/arm/mve-vorn.d: New test.

>          * testsuite/gas/arm/mve-vorn.s: New test.

>          * testsuite/gas/arm/mve-vorr.d: New test.

>          * testsuite/gas/arm/mve-vorr.s: New test.

>          * testsuite/gas/arm/mve-vpnot.d: New test.

>          * testsuite/gas/arm/mve-vpnot.s: New test.

>          * testsuite/gas/arm/mve-vpsel.d: New test.

>          * testsuite/gas/arm/mve-vpsel.s: New test.

>          * testsuite/gas/arm/mve-vpt.d: New test.

>          * testsuite/gas/arm/mve-vpt.s: New test.

>          * testsuite/gas/arm/mve-vqabsneg.s: New test.

>          * testsuite/gas/arm/mve-vqaddsub.d: New test.

>          * testsuite/gas/arm/mve-vqaddsub.s: New test.

>          * testsuite/gas/arm/mve-vqdmladh.d: New test.

>          * testsuite/gas/arm/mve-vqdmladh.s: New test.

>          * testsuite/gas/arm/mve-vqdmlah.d: New test.

>          * testsuite/gas/arm/mve-vqdmlah.s: New test.

>          * testsuite/gas/arm/mve-vqdmlash.d: New test.

>          * testsuite/gas/arm/mve-vqdmlash.s: New test.

>          * testsuite/gas/arm/mve-vqdmlsdh.d: New test.

>          * testsuite/gas/arm/mve-vqdmlsdh.s: New test.

>          * testsuite/gas/arm/mve-vqdmulh.d: New test.

>          * testsuite/gas/arm/mve-vqdmulh.s: New test.

>          * testsuite/gas/arm/mve-vqdmull.d: New test.

>          * testsuite/gas/arm/mve-vqdmull.s: New test.

>          * testsuite/gas/arm/mve-vqmovn.d: New test.

>          * testsuite/gas/arm/mve-vqmovn.s: New test.

>          * testsuite/gas/arm/mve-vqrshl.d: New test.

>          * testsuite/gas/arm/mve-vqrshl.s: New test.

>          * testsuite/gas/arm/mve-vqrshrn.d: New test.

>          * testsuite/gas/arm/mve-vqrshrn.s: New test.

>          * testsuite/gas/arm/mve-vqshl.d: New test.

>          * testsuite/gas/arm/mve-vqshl.s: New test.

>          * testsuite/gas/arm/mve-vrev.d: New test.

>          * testsuite/gas/arm/mve-vrev.s: New test.

>          * testsuite/gas/arm/mve-vrint.d: New test.

>          * testsuite/gas/arm/mve-vrint.s: New test.

>          * testsuite/gas/arm/mve-vrmlaldavh.d: New test.

>          * testsuite/gas/arm/mve-vrmlaldavh.s: New test.

>          * testsuite/gas/arm/mve-vrshl.d: New test.

>          * testsuite/gas/arm/mve-vrshl.s: New test.

>          * testsuite/gas/arm/mve-vsbc.d: New test.

>          * testsuite/gas/arm/mve-vsbc.s: New test.

>          * testsuite/gas/arm/mve-vshl.d: New test.

>          * testsuite/gas/arm/mve-vshl.s: New test.

>          * testsuite/gas/arm/mve-vshlc.d: New test.

>          * testsuite/gas/arm/mve-vshlc.s: New test.

>          * testsuite/gas/arm/mve-vshll.d: New test.

>          * testsuite/gas/arm/mve-vshll.s: New test.

>          * testsuite/gas/arm/mve-vshr.d: New test.

>          * testsuite/gas/arm/mve-vshr.s: New test.

>          * testsuite/gas/arm/mve-vshrn.d: New test.

>          * testsuite/gas/arm/mve-vshrn.s: New test.

>          * testsuite/gas/arm/mve-vsli.d: New test.

>          * testsuite/gas/arm/mve-vsli.s: New test.

>          * testsuite/gas/arm/mve-vsri.d: New test.

>          * testsuite/gas/arm/mve-vsri.s: New test.

>          * testsuite/gas/arm/mve-vstld.d: New test.

>          * testsuite/gas/arm/mve-vstld.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-1.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-1.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-2.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-2.s: New test.

>          * testsuite/gas/arm/mve-vstrldr-3.d: New test.

>          * testsuite/gas/arm/mve-vstrldr-3.s: New test.
Nick Clifton May 2, 2019, 10:03 a.m. | #7
Hi Andre,

> The reason to split the testing is because we use assembly macros to generate extensive testing, which leads to massive 'expected result' files. Which would require zipping most of the patches to be able to send them over email. So instead we decided to collate all positive testing into one patch and only zip that one. The negative tests are smaller and have been included per relevant patch.


With the whole patch series applied to today's binutils mainline sources,
I am seeing three new assembler testsuite failures for an arm-eabi toolchain.
(I have not checked other arm toolchains yet).  The failures are:

  Running gas/testsuite/gas/arm/arm.exp ...
  FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions
  FAIL: bad MVE WLSTP, DLSTP and LETP instructions
  FAIL: MVE tail predicated low-overhead loop instructions

And looking in the log I see:

  gas/testsuite/gas/arm/armv8_1-m-loloop.s: Assembler messages:
  gas/testsuite/gas/arm/armv8_1-m-loloop.s:10: Error: branch out of range or not a multiple of 2
  FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions

and:

  extra lines in tmpdir/ld.messages starting with "^gas/testsuite/gas/arm/mve-tailpredloop-bad.s:27:   
  Error: branch out of range or not a multiple of 2$"
  EOF from gas/testsuite/gas/arm/mve-tailpredloop-bad.l
  FAIL: bad MVE WLSTP, DLSTP and LETP instructions

and:

  gas/arm/mve-tailpredloop.s:16: Error: branch out of range or not a multiple of 2
  gas/testsuite/gas/arm/mve-tailpredloop.s:17: Error: branch out of range or not a multiple of 2>, no expected output
  FAIL: MVE tail predicated low-overhead loop instructions

Possibly these are the result of my "fixing" the compilation problem in arm-dis.c
mentioned in a previous email, but I would appreciate it if you could investigate.

Cheers
  Nick
Nick Clifton May 2, 2019, 10:18 a.m. | #8
Hi Andre,

> This patch series adds support for all M-profile Vector Extension(MVE) instructions to GAS and Objdump. 


I just noticed that the patch series does not include additions to the 
gas/NEWS and binutils/NEWS files, mentioning support for this architecture
extension.  Please could you add that ?

Cheers
  Nick
Nick Clifton May 2, 2019, 1:39 p.m. | #9
Hi Andre,

  This is just a quick note to say that I have found no other
  issues with the rest of your patch series, so once the items
  I have already mentioned are resolved I will be happy to approve
  the series.

Cheers
  Nick