[ARM,0/16] Add support for Armv8.1-M Mainline

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  • Add support for Armv8.1-M Mainline
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Message

Andre Vieira (lists) April 4, 2019, 1:24 p.m.
Hello,

This is a patch series to implement support for Armv8.1-M Mainline. The 
specifications for the Armv8.1-M Mainline can be found in 
https://developer.arm.com/docs/ddi0553/latest

This patch series does not cover M-profile Vector Extension (MVE) 
support, this will be implemented in a follow-up patch series.

Andre Vieira (16):
[PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI
[PATCH, GAS, ARM, 2/16] Add architecture extension support for Armv8.1-M 
Mainline
[PATCH, binutils, ARM, 3/16] BF insns infrastructure with new 
bfd_reloc_code_real for fallback branch
[PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of 
relocs in struct arm_it
[PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global 
reloc R_ARM_THM_BF16
[PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
[PATCH, binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M 
Mainline
[PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc 
R_ARM_THM_BF18
[PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
[PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global 
reloc R_ARM_THM_BF12
[PATCH, binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline
[PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions for 
Armv8.1-M Mainline
[PATCH, binutils, ARM, 13/16] Add support for CLRM
[PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table 
entries
[PATCH, binutils, ARM, 15/16] Add support for VSCCLRM
[PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system 
registers

Comments

Nick Clifton April 11, 2019, 10:04 a.m. | #1
Hi Andre,

> This is a patch series to implement support for Armv8.1-M Mainline. The specifications for the Armv8.1-M Mainline can be found in https://developer.arm.com/docs/ddi0553/latest


The patch series looks fine to me, apart from two small problems:

1) It introduces some assembler testsuite failures for non-ELF based
ARM toolchains:

Checking Binutils in: arm-wince-pe ... 
  GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

2) It introduces some assembler and linker testsuite failures for 
big-endian ARM toolchains:

Checking Binutils in: armeb-eabi ... 
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead
  LD REGRESSION: Armv8.1-M Mainline BF  
  LD REGRESSION: Armv8.1-M Mainline BFL  
  LD REGRESSION: Armv8.1-M Mainline BFCSEL  
  LD REGRESSION: Armv8.1-M Mainline BF  
  LD REGRESSION: Armv8.1-M Mainline BFL  
  LD REGRESSION: Armv8.1-M Mainline BFCSEL  
  LD REGRESSION: Armv8.1-M Mainline BF  
  LD REGRESSION: Armv8.1-M Mainline BFL  
  LD REGRESSION: Armv8.1-M Mainline BFCSEL  
  LD REGRESSION: Armv8.1-M Mainline BF  
  LD REGRESSION: Armv8.1-M Mainline BFL  
  LD REGRESSION: Armv8.1-M Mainline BFCSEL  

Would you mind taking a look at these please ?

Cheers
  Nick

PS.  This was from testing with the entire patch series applied.
I have not narrowed down the specific patches that introduce the
new failures, but I assume that it will be simple for you to do
this yourself.
Andre Vieira (lists) April 12, 2019, 10:39 a.m. | #2
Hi Nick,

Thanks for that! Most of them were testisms.  Though there was an actual 
issue with big-endian and the LE instruction.  I replied to each 
relevant patch with an updated version.

Cheers,
Andre

On 11/04/2019 11:04, Nick Clifton wrote:
> Hi Andre,

> 

>> This is a patch series to implement support for Armv8.1-M Mainline. The specifications for the Armv8.1-M Mainline can be found in https://developer.arm.com/docs/ddi0553/latest

> 

> The patch series looks fine to me, apart from two small problems:

> 

> 1) It introduces some assembler testsuite failures for non-ELF based

> ARM toolchains:

> 

> Checking Binutils in: arm-wince-pe ...

>    GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    GAS REGRESSION: Valid Armv8.1-M Mainline BF instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFCSEL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline BFL instruction

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

> 

> 2) It introduces some assembler and linker testsuite failures for

> big-endian ARM toolchains:

> 

> Checking Binutils in: armeb-eabi ...

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    GAS REGRESSION: Valid Armv8.1-M Mainline Low Overhead

>    LD REGRESSION: Armv8.1-M Mainline BF

>    LD REGRESSION: Armv8.1-M Mainline BFL

>    LD REGRESSION: Armv8.1-M Mainline BFCSEL

>    LD REGRESSION: Armv8.1-M Mainline BF

>    LD REGRESSION: Armv8.1-M Mainline BFL

>    LD REGRESSION: Armv8.1-M Mainline BFCSEL

>    LD REGRESSION: Armv8.1-M Mainline BF

>    LD REGRESSION: Armv8.1-M Mainline BFL

>    LD REGRESSION: Armv8.1-M Mainline BFCSEL

>    LD REGRESSION: Armv8.1-M Mainline BF

>    LD REGRESSION: Armv8.1-M Mainline BFL

>    LD REGRESSION: Armv8.1-M Mainline BFCSEL

> 

> Would you mind taking a look at these please ?

> 

> Cheers

>    Nick

> 

> PS.  This was from testing with the entire patch series applied.

> I have not narrowed down the specific patches that introduce the

> new failures, but I assume that it will be simple for you to do

> this yourself.

>
Nick Clifton April 12, 2019, 1:50 p.m. | #3
Hi Andre,

> Thanks for that! Most of them were testisms.  Though there was an actual issue with big-endian and the LE instruction.  I replied to each relevant patch with an updated version.


Great - in which case the patch series is approved.  Do you need to me ACK each
of them individually, or is this approval enough ?

Cheers
  Nick
Andre Vieira (lists) April 15, 2019, 9:41 a.m. | #4
Hi Nick,

No need, Ill start upstreaming them. Thank you for the review.

Cheers,
Andre
-----Original Message-----
From: Nick Clifton <nickc@redhat.com> 

Sent: 12 April 2019 14:51
To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>; binutils@sourceware.org
Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline

Hi Andre,

> Thanks for that! Most of them were testisms.  Though there was an actual issue with big-endian and the LE instruction.  I replied to each relevant patch with an updated version.


Great - in which case the patch series is approved.  Do you need to me ACK each of them individually, or is this approval enough ?

Cheers
  Nick
Alan Modra April 16, 2019, 1:57 a.m. | #5
These failures remain.
arm-pe  +FAIL: Valid Armv8.1-M Mainline BF instruction
arm-pe  +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction
arm-pe  +FAIL: Valid Armv8.1-M Mainline BFL instruction
arm-pe  +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions
arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation
arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation

-- 
Alan Modra
Australia Development Lab, IBM
Andre Vieira (lists) April 16, 2019, 11:52 a.m. | #6
Hi Alan,

Thanks for the heads up.  I am on holidays so I don't have much time to look at this right now. But after a quick look I think the arm-pe fails are due to objdump printing the branch targets in a different format. I'll double-check later, but it should be a case of accepting both answers.

The VxWorks failures seem to be related to the relocations. I did a quick search but couldn't determine whether VxWorks uses Elf binary format. Do you reckon VxWorks should support this elf relocation? If so I'll need to look at it a bit further, otherwise I'll skip the relocation tests for VxWorks.

Cheers,
Andre

-----Original Message-----
From: Alan Modra <amodra@gmail.com> 

Sent: 16 April 2019 02:58
To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>
Cc: nickc@redhat.com; binutils@sourceware.org; nd <nd@arm.com>
Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline

These failures remain.
arm-pe  +FAIL: Valid Armv8.1-M Mainline BF instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline BFL instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation

--
Alan Modra
Australia Development Lab, IBM
Alan Modra April 16, 2019, 12:36 p.m. | #7
On Tue, Apr 16, 2019 at 11:52:19AM +0000, Andre Simoes Dias Vieira wrote:
> Hi Alan,

> 

> Thanks for the heads up.  I am on holidays so I don't have much time to look at this right now. But after a quick look I think the arm-pe fails are due to objdump printing the branch targets in a different format. I'll double-check later, but it should be a case of accepting both answers.

> 

> The VxWorks failures seem to be related to the relocations. I did a quick search but couldn't determine whether VxWorks uses Elf binary format. Do you reckon VxWorks should support this elf relocation? If so I'll need to look at it a bit further, otherwise I'll skip the relocation tests for VxWorks.


VxWorks uses ELF.  The difference is that unlike other ARM targets,
arm-vxworks uses rela style relocations.  Very likely your new reloc
processing is broken for rela.  ie. You shouldn't just sweep this
under the rug.  ;-)

> Cheers,

> Andre

> 

> -----Original Message-----

> From: Alan Modra <amodra@gmail.com> 

> Sent: 16 April 2019 02:58

> To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>

> Cc: nickc@redhat.com; binutils@sourceware.org; nd <nd@arm.com>

> Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline

> 

> These failures remain.

> arm-pe  +FAIL: Valid Armv8.1-M Mainline BF instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline BFL instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation

> 

> --

> Alan Modra

> Australia Development Lab, IBM


-- 
Alan Modra
Australia Development Lab, IBM
Andre Vieira (lists) May 1, 2019, 9:32 a.m. | #8
Hello,

After some investigation I found there were more things wrong with the 
way we handled the branch future relocations.  I fixed these and added a 
linker test for ELF targets (and a duplicate entry for vxworks as we 
seem to skip other elf linker tests for it).

As for the vxworks failures Alan spotted, I believe this is due to the 
relocations being treated differently, as you pointed out one uses REL 
and the other RELA. This leads to different relocation encodings. So for 
instance when a REL target encodes a relocation for 'target' it seems to 
do so with:
A = 0
S = target

whereas for RELA it uses:
A = 4
S = target-4

These do get handled correctly by the linker as shown in the test added 
for vxworks and other elf targets.  I also checked other similar 
relocations, such as the R_ARM_THM_JUMP24, and these behave the same way.

As a side effect, this patch also removes the unnecessary 
'get_value_helper' function thus also fixing PR/target 24460 @Sudi 
please do not commit your earlier fix.

Tested on arm-none-eabi, arm-vxworks, arm-wince-pe, and arm-pe.

Is this OK for trunk?

bfd/ChangeLog:
2019-04-30  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         PR/target 24460
         * elf32-arm.c (get_value_helper): Remove.
         (elf32_arm_final_link_relocate): Fix branch future relocations.

gas/ChangeLog:
2019-04-30  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target
         naming conventions.
         * testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
         * testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
         * testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
         * testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
         * testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
         * testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
         * testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.

ld/ChangeLog:
2019-04-30  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * testsuite/ld-arm/arm-elf.exp: Add tests
         * testsuite/ld-arm/bfs-0.s: New test.
         * testsuite/ld-arm/bfs-1.s: New test.
         * testsuite/ld-arm/branch-futures.d: New test.

On 16/04/2019 13:36, Alan Modra wrote:
> On Tue, Apr 16, 2019 at 11:52:19AM +0000, Andre Simoes Dias Vieira wrote:

>> Hi Alan,

>>

>> Thanks for the heads up.  I am on holidays so I don't have much time to look at this right now. But after a quick look I think the arm-pe fails are due to objdump printing the branch targets in a different format. I'll double-check later, but it should be a case of accepting both answers.

>>

>> The VxWorks failures seem to be related to the relocations. I did a quick search but couldn't determine whether VxWorks uses Elf binary format. Do you reckon VxWorks should support this elf relocation? If so I'll need to look at it a bit further, otherwise I'll skip the relocation tests for VxWorks.

> 

> VxWorks uses ELF.  The difference is that unlike other ARM targets,

> arm-vxworks uses rela style relocations.  Very likely your new reloc

> processing is broken for rela.  ie. You shouldn't just sweep this

> under the rug.  ;-)

> 

>> Cheers,

>> Andre

>>

>> -----Original Message-----

>> From: Alan Modra <amodra@gmail.com>

>> Sent: 16 April 2019 02:58

>> To: Andre Simoes Dias Vieira <Andre.SimoesDiasVieira@arm.com>

>> Cc: nickc@redhat.com; binutils@sourceware.org; nd <nd@arm.com>

>> Subject: Re: [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline

>>

>> These failures remain.

>> arm-pe  +FAIL: Valid Armv8.1-M Mainline BF instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline BFCSEL instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline BFL instruction arm-pe  +FAIL: Valid Armv8.1-M Mainline Low Overhead loop instructions arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BF instruction with relocation arm-vxworks  +FAIL: Valid Armv8.1-M Mainline BFL instruction with relocation

>>

>> --

>> Alan Modra

>> Australia Development Lab, IBM

>
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 337961d26e16c6458f41d54b2e8dbe6891a5017c..a4fd7de7aa2354dd25ebca8a5c222716a5468197 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -10293,59 +10293,6 @@ identify_add_or_sub (bfd_vma insn)
   return 0;
 }
 
-/* Helper function to compute the Addend for Armv8.1-M Mainline relocations.  */
-static bfd_vma
-get_value_helper (bfd_vma plt_offset,
-		  asection *splt,
-		  asection *input_section,
-		  asection *sym_sec,
-		  struct elf_link_hash_entry * h,
-		  struct bfd_link_info *info,
-		  bfd *input_bfd,
-		  Elf_Internal_Rela *rel,
-		  const char *sym_name,
-		  unsigned char st_type,
-		  struct elf32_arm_link_hash_table *globals,
-		  bfd_boolean *unresolved_reloc_p)
-{
-  bfd_vma value = 0;
-  enum arm_st_branch_type branch_type;
-  enum elf32_arm_stub_type stub_type = arm_stub_none;
-  struct elf32_arm_stub_hash_entry *stub_entry;
-  struct elf32_arm_link_hash_entry *hash
-    = (struct elf32_arm_link_hash_entry *)h;
-
-
-  if (plt_offset != (bfd_vma) -1)
-    {
-      value = (splt->output_section->vma
-	       + splt->output_offset
-	       + plt_offset);
-      value -= PLT_THUMB_STUB_SIZE;
-      *unresolved_reloc_p = FALSE;
-    }
-
-  stub_type = arm_type_of_stub (info, input_section, rel,
-				st_type, &branch_type,
-				hash, value, sym_sec,
-				input_bfd, sym_name);
-
-  if (stub_type != arm_stub_none)
-    {
-      stub_entry = elf32_arm_get_stub_entry (input_section,
-					     sym_sec, h,
-					     rel, globals,
-					     stub_type);
-	    if (stub_entry != NULL)
-	      {
-		value = (stub_entry->stub_offset
-			 + stub_entry->stub_sec->output_offset
-			 + stub_entry->stub_sec->output_section->vma);
-	      }
-	  }
-  return value;
-}
-
 /* Perform a relocation as part of a final link.  */
 
 static bfd_reloc_status_type
@@ -12968,14 +12915,10 @@ elf32_arm_final_link_relocate (reloc_howto_type *	    howto,
 	    addend |= (immC << 1);
 	    addend |= 1;
 	    /* Sign extend.  */
-	    addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
+	    signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
 	  }
 
-	value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
-				  info, input_bfd, rel, sym_name, st_type,
-				  globals, unresolved_reloc_p);
-
-	relocation  = value + addend;
+	relocation  = value + signed_addend;
 	relocation -= (input_section->output_section->vma
 		       + input_section->output_offset
 		       + rel->r_offset);
@@ -13014,13 +12957,10 @@ elf32_arm_final_link_relocate (reloc_howto_type *	    howto,
 	    addend |= 1;
 	    /* Sign extend.  */
 	    addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
+	    signed_addend = addend;
 	  }
 
-	value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
-				  info, input_bfd, rel, sym_name, st_type,
-				  globals, unresolved_reloc_p);
-
-	relocation  = value + addend;
+	relocation  = value + signed_addend;
 	relocation -= (input_section->output_section->vma
 		       + input_section->output_offset
 		       + rel->r_offset);
@@ -13059,13 +12999,10 @@ elf32_arm_final_link_relocate (reloc_howto_type *	    howto,
 	    addend |= 1;
 	    /* Sign extend.  */
 	    addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
+	    signed_addend = addend;
 	  }
 
-	value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
-				  info, input_bfd, rel, sym_name, st_type,
-				  globals, unresolved_reloc_p);
-
-	relocation  = value + addend;
+	relocation  = value + signed_addend;
 	relocation -= (input_section->output_section->vma
 		       + input_section->output_offset
 		       + rel->r_offset);
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
index e429c136f2ea7818de2a7479a21f0cc6bc0702e1..bdb265c5a3aa8cc4f4d0112562249b559d468784 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BF instruction with relocation
+#name: Valid Armv8.1-M Mainline BF instruction with REL
 #as: -march=armv8.1-m.main
 #objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-* 
+#skip: *-*-pe *-wince-* *-vxworks
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
new file mode 100644
index 0000000000000000000000000000000000000000..d363d098523ae5ef54870f595b7aa8dd1bc7a226
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BF instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source:armv8_1-m-bf-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e001 	bf	2, 00000004 <.target\+0x4>
+			0: R_ARM_THM_BF16	.target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
index dd30b2a2ff1d35cd58299813614ec5a79cbcdadf..99de065903bca1ffc407b043a0c9cd554c44a25e 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bf.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -5,9 +5,9 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f0c0 e803 	bf	2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f0c0 e803 	bf	2, 0000000a <.*>
 0[0-9a-f]+ <[^>]+> 4609      	mov	r1, r1
-0[0-9a-f]+ <[^>]+> f140 e801 	bf	4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f140 e801 	bf	4, 0000000c <.*>
 0[0-9a-f]+ <[^>]+> 460a      	mov	r2, r1
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
index a498f06cd3e68370b737976ac3453855852f5b58..b66e9295f59e164533c2dd928fff5173ec6778be 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d
@@ -5,8 +5,8 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 e803 	bfcsel	2, 0000000a <foo\+0xa>, 4, eq
+0[0-9a-f]+ <[^>]+> f080 e803 	bfcsel	2, 0000000a <.*>, 4, eq
 0[0-9a-f]+ <[^>]+> 4609      	mov	r1, r1
-0[0-9a-f]+ <[^>]+> d000      	beq.n	0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> d000      	beq.n	0000000a <.*>
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
index 13c6bf1caa5cb68844bd4b4d33acef9223edfa03..951074cff0962e5ee13ebf8219a0ab515df60f5f 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d
@@ -1,7 +1,7 @@
-#name: Valid Armv8.1-M Mainline BFL instruction with relocation
+#name: Valid Armv8.1-M Mainline BFL instruction with REL
 #as: -march=armv8.1-m.main
 #objdump: -dr --prefix-addresses --show-raw-insn
-#skip: *-*-pe *-wince-*
+#skip: *-*-pe *-wince-* *-vxworks
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
new file mode 100644
index 0000000000000000000000000000000000000000..291d10b4af82d376a260d06ee6c434d6fe1b4f6a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
@@ -0,0 +1,12 @@
+#name: Valid Armv8.1-M Mainline BFL instruction with RELA
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: armv8_1-m-bfl-rel.s
+#noskip: *-vxworks
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f080 c001 	bfl	2, 00000004 <.target\+0x4>
+			0: R_ARM_THM_BF18	.target-0x4
+
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
index e15636b359f8db2829e46706f9cd0ea3e1d45500..b28d0b111e362c130b5c17b57749f1170c845e50 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-bfl.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d
@@ -5,9 +5,9 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f080 c803 	bfl	2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> f080 c803 	bfl	2, 0000000a <.*>
 0[0-9a-f]+ <[^>]+> 4608      	mov	r0, r1
-0[0-9a-f]+ <[^>]+> f100 c801 	bfl	4, 0000000c <foo\+0xc>
+0[0-9a-f]+ <[^>]+> f100 c801 	bfl	4, 0000000c <.*>
 0[0-9a-f]+ <[^>]+> 460a      	mov	r2, r1
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 0[0-9a-f]+ <[^>]+> 4614      	mov	r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
index 1e02b82651f7127c5c98d3518a0a653445db4c9a..20506c692005d40e3ed328a0f27251e8663e27ed 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-loloop.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d
@@ -6,12 +6,12 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f042 c00d 	wls	lr, r2, 0000001c <foo\+0x1c>
+0[0-9a-f]+ <[^>]+> f042 c00d 	wls	lr, r2, 0000001c <.*>
 0[0-9a-f]+ <[^>]+> f042 e001 	dls	lr, r2
 0[0-9a-f]+ <[^>]+> f04e e001 	dls	lr, lr
-0[0-9a-f]+ <[^>]+> f00f c009 	le	lr, 00000000 <foo>
-0[0-9a-f]+ <[^>]+> f02f c00b 	le	00000000 <foo>
-0[0-9a-f]+ <[^>]+> f00f c24b 	le	lr, fffffb84 <foo\+0xfffffb84>
-0[0-9a-f]+ <[^>]+> f02f c007 	le	00000010 <foo\+0x10>
+0[0-9a-f]+ <[^>]+> f00f c009 	le	lr, 00000000 <.*>
+0[0-9a-f]+ <[^>]+> f02f c00b 	le	00000000 <.*>
+0[0-9a-f]+ <[^>]+> f00f c24b 	le	lr, fffffb84 <.*>
+0[0-9a-f]+ <[^>]+> f02f c007 	le	00000010 <.*>
 0[0-9a-f]+ <[^>]+> 4613      	mov	r3, r2
 #...
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 5471895e63a68c0ee5e9c9644564e7b9235a4184..7d3217f87a26303f776d2390cdab9a426ef3d3e9 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -42,6 +42,11 @@ if {[istarget "arm-*-vxworks"]} {
 	 "" {vxworks2.s}
 	 {{readelf --segments vxworks2-static.sd}}
 	 "vxworks2"}
+	{"Branch future relocations for armv8.1-m.main target"
+	  "-static -T arm.ld"
+	  "" "" {bfs-0.s bfs-1.s}
+	  {{objdump -dw branch-futures.d}}
+	 "branch-futures"}
     }
     run_ld_link_tests $armvxworkstests
     run_dump_test "vxworks1-static"
@@ -260,6 +265,10 @@ set armelftests_common_3 {
     {"ADDS thumb1 relocations for armv7-m target" "-static -T arm.ld" "" "" {thumb1-adds-armv7-m.s}
      {{objdump -dw thumb1-adds.d}}
      "thumb1-adds"}
+    {"Branch future relocations for armv8.1-m.main target" "-static -T arm.ld"
+      "" "" {bfs-0.s bfs-1.s}
+      {{objdump -dw branch-futures.d}}
+     "branch-futures"}
 }
 
 run_ld_link_tests $armelftests_common_1
diff --git a/ld/testsuite/ld-arm/bfs-0.s b/ld/testsuite/ld-arm/bfs-0.s
new file mode 100644
index 0000000000000000000000000000000000000000..844417a56c6f35e56716ef929d3a81f09b7615b2
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfs-0.s
@@ -0,0 +1,12 @@
+.arch armv8.1-m.main
+.text
+.syntax unified
+.thumb
+future:
+	bf	branch, target
+	bfcsel	branch, target, else, eq
+	bfl	branch, target
+	add	r0, r0, r1
+branch:
+	b	target
+else:
diff --git a/ld/testsuite/ld-arm/bfs-1.s b/ld/testsuite/ld-arm/bfs-1.s
new file mode 100644
index 0000000000000000000000000000000000000000..2b72819598edf1509d12cf8b01e5d2028bddda38
--- /dev/null
+++ b/ld/testsuite/ld-arm/bfs-1.s
@@ -0,0 +1,9 @@
+.arch armv8.1-m.main
+.text
+.syntax unified
+.thumb
+.global _start
+.global target
+_start:
+target:
+	add	r0, r0, r1
diff --git a/ld/testsuite/ld-arm/branch-futures.d b/ld/testsuite/ld-arm/branch-futures.d
new file mode 100644
index 0000000000000000000000000000000000000000..427ecce62a4d2f22b3b64fe03435802845c567cf
--- /dev/null
+++ b/ld/testsuite/ld-arm/branch-futures.d
@@ -0,0 +1,17 @@
+
+.*:     file format elf32-.*
+
+
+Disassembly of section .text:
+
+0[0-9a-f]+ <future>:
+    [0-9a-f]+:	f2c0 e807 	bf	a, 8012 <_start>
+    [0-9a-f]+:	f182 e805 	bfcsel	6, 8012 <_start>, a, eq
+    [0-9a-f]+:	f080 c803 	bfl	2, 8012 <_start>
+    [0-9a-f]+:	4408      	add	r0, r1
+
+0[0-9a-f]+ <branch>:
+    [0-9a-f]+:	f000 b800 	b.w	8012 <_start>
+
+0[0-9a-f]+ <_start>:
+    [0-9a-f]+:	4408      	add	r0, r1
Alan Modra May 2, 2019, 1:21 a.m. | #9
On Wed, May 01, 2019 at 10:32:17AM +0100, Andre Vieira (lists) wrote:
> As for the vxworks failures Alan spotted, I believe this is due to the

> relocations being treated differently, as you pointed out one uses REL and

> the other RELA. This leads to different relocation encodings. So for

> instance when a REL target encodes a relocation for 'target' it seems to do

> so with:

> A = 0

> S = target

> 

> whereas for RELA it uses:

> A = 4

> S = target-4


No, this is confused.  The "A" you are showing here is the value
displayed by objdump after decoding.  This is completely irrelevant.
In actual fact the value of "A", the addend as per the ABI, is -4 for
both REL and RELA.  "S" is the symbol, ie. "target" (there is no such
thing as S = target-4).

For your first testcase, armv8_1-m-bf-rel.d, you expect
f0df e7ff 	bf	2, 00000000 <.target>
			0: R_ARM_THM_BF16	.target
If you squint at that instruction long enough, you'll see that the
instruction (split) field is indeed -4, and since addends are taken
from the instruction for REL relocations, "A" is -4.

armv8_1-m-bf-rela.d expects
f0c0 e001 	bf	2, 00000004 <.target\+0x4>
			0: R_ARM_THM_BF16	.target-0x4
Here the instruction field is left as 0 (the value of the field
doesn't matter), and "A" of -4 is taken from the RELA relocation
addend.

I believe the reason for the -4 addend is that ARM processors
calculate branch targets relative to the insn PC plus 4 for 4-byte
insns.  So I don't have any problem with the patch itself, but wanted
to clear up any confusion in your patch explanation.  Approval of the
patch will be handled by one of the ARM maintainers.

-- 
Alan Modra
Australia Development Lab, IBM
Andre Vieira (lists) May 15, 2019, 3:34 p.m. | #10
Ping, this one still needs an OK.

Cheers,
Andre

On 02/05/2019 02:21, Alan Modra wrote:
> On Wed, May 01, 2019 at 10:32:17AM +0100, Andre Vieira (lists) wrote:

>> As for the vxworks failures Alan spotted, I believe this is due to the

>> relocations being treated differently, as you pointed out one uses REL and

>> the other RELA. This leads to different relocation encodings. So for

>> instance when a REL target encodes a relocation for 'target' it seems to do

>> so with:

>> A = 0

>> S = target

>>

>> whereas for RELA it uses:

>> A = 4

>> S = target-4

> 

> No, this is confused.  The "A" you are showing here is the value

> displayed by objdump after decoding.  This is completely irrelevant.

> In actual fact the value of "A", the addend as per the ABI, is -4 for

> both REL and RELA.  "S" is the symbol, ie. "target" (there is no such

> thing as S = target-4).

> 

> For your first testcase, armv8_1-m-bf-rel.d, you expect

> f0df e7ff 	bf	2, 00000000 <.target>

> 			0: R_ARM_THM_BF16	.target

> If you squint at that instruction long enough, you'll see that the

> instruction (split) field is indeed -4, and since addends are taken

> from the instruction for REL relocations, "A" is -4.

> 

> armv8_1-m-bf-rela.d expects

> f0c0 e001 	bf	2, 00000004 <.target\+0x4>

> 			0: R_ARM_THM_BF16	.target-0x4

> Here the instruction field is left as 0 (the value of the field

> doesn't matter), and "A" of -4 is taken from the RELA relocation

> addend.

> 

> I believe the reason for the -4 addend is that ARM processors

> calculate branch targets relative to the insn PC plus 4 for 4-byte

> insns.  So I don't have any problem with the patch itself, but wanted

> to clear up any confusion in your patch explanation.  Approval of the

> patch will be handled by one of the ARM maintainers.

>
Nick Clifton May 20, 2019, 10:31 a.m. | #11
Hi Andre,

> Ping, this one still needs an OK.


oopsie...

Patch series approved - please apply.

Cheers
  Nick